# MEIC: Re-thinking RTL Debug Automation using LLMs

arXiv: https://arxiv.org/abs/2405.06840 · HTML: https://mlsanity.com/paper/2405.06840/

## Key facts

- Cited by 25 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 10 May 2024.

## Built on by (most cited first, 25 of 25)

- [A Survey of Research in Large Language Models for Electronic Design Automation](https://mlsanity.com/paper/2501.09655/) (2025)
- [VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation](https://mlsanity.com/paper/2504.15659/) (2025)
- [Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog](https://mlsanity.com/paper/2409.15186/) (2024)
- [From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification](https://mlsanity.com/paper/2504.19959/) (2025)
- [Revolution or Hype? Seeking the Limits of Large Models in Hardware Design](https://mlsanity.com/paper/2509.04905/) (2025)
- [Understanding and Mitigating Errors of LLM-Generated RTL Code](https://mlsanity.com/paper/2508.05266/) (2025)
- [iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs](https://mlsanity.com/paper/2505.22086/) (2025)
- [Image2Net: Datasets, Benchmark and Hybrid Framework to Convert Analog Circuit Diagrams into Netlists](https://mlsanity.com/paper/2508.13157/) (2025)
- [ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs](https://mlsanity.com/paper/2604.02811/) (2026)
- [MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Models](https://mlsanity.com/paper/2505.11963/) (2025)
- [FVDebug: An LLM-Driven Debugging Assistant for Automated Root Cause Analysis of Formal Verification Failures](https://mlsanity.com/paper/2510.15906/) (2025)
- [GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation](https://mlsanity.com/paper/2601.07593/) (2026)
- [CktEvo: Repository-Level RTL Code Benchmark for Design Evolution](https://mlsanity.com/paper/2603.08718/) (2026)
- [R3A: Reliable RTL Repair Framework with Multi-Agent Fault Localization and Stochastic Tree-of-Thoughts Patch Generation](https://mlsanity.com/paper/2511.20090/) (2025)
- [AgenticTCAD: A LLM-based Multi-Agent Framework for Automated TCAD Code Generation and Device Optimization](https://mlsanity.com/paper/2512.23742/) (2025)
- [HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs](https://mlsanity.com/paper/2604.27643/) (2026)
- [BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks](https://mlsanity.com/paper/2504.05180/) (2025)
- [HDLxGraph: Bridging Large Language Models and HDL Repositories via HDL Graph Databases](https://mlsanity.com/paper/2505.15701/) (2025)
- [VeriPilot: An LLM-Powered Verilog Debugging Framework](https://mlsanity.com/paper/2606.23759/) (2026)
- [Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors](https://mlsanity.com/paper/2503.02335/) (2025)
- [DUET: Agentic Design Understanding via Experimentation and Testing](https://mlsanity.com/paper/2512.06247/) (2025)
- [SecureRAG-RTL: A Retrieval-Augmented, Multi-Agent, Zero-Shot LLM-Driven Framework for Hardware Vulnerability Detection](https://mlsanity.com/paper/2603.05689/) (2026)
- [Agentic Electronic Design Automation: A Handoff Perspective](https://mlsanity.com/paper/2606.19795/) (2026)
- [LLM for EDA in Front-End Design: Challenges and Opportunities](https://mlsanity.com/paper/2607.09616/) (2026)
- [SeqFeed: Improving Agentic RTL Code Generation with Sequential Behavior Feedback](https://mlsanity.com/paper/2608.16934/) (2026)

## Abstract (arXiv)

The deployment of Large Language Models (LLMs) for code debugging (e.g., C and Python) is widespread, benefiting from their ability to understand and interpret intricate concepts. However, in the semiconductor industry, utilising LLMs to debug Register Transfer Level (RTL) code is still insufficient, largely due to the underrepresentation of RTL-specific data in training sets. This work introduces a novel framework, Make Each Iteration Count (MEIC), which contrasts with traditional one-shot LLM-based debugging methods that heavily rely on prompt engineering, model tuning, and model training. MEIC utilises LLMs in an iterative process to overcome the limitation of LLMs in RTL code debugging, which is suitable for identifying and correcting both syntax and function errors, while effectively managing the uncertainties inherent in LLM operations. To evaluate our framework, we provide an open-source dataset comprising 178 common RTL programming errors. The experimental results demonstrate that the proposed debugging framework achieves fix rate of 93% for syntax errors and 78% for function errors, with up to 48x speedup in debugging processes when compared with experienced engineers. The Repo. of dataset and code: https://anonymous.4open.science/r/Verilog-Auto-Debug-6E7F/.