# TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans

arXiv: https://arxiv.org/abs/2405.05590 · HTML: https://mlsanity.com/paper/2405.05590/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 15 of its 75 references that are in the map.
- First posted on arXiv 9 May 2024.

## Builds on (most cited first, 15 of 15)

- [ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning](https://mlsanity.com/paper/2208.12897/) (2022)
- [TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection](https://mlsanity.com/paper/2301.11804/) (2023)
- [SAIL: Machine Learning Guided Structural Analysis Attack on Hardware Obfuscation](https://mlsanity.com/paper/1809.10743/) (2018)
- [MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-based Link Prediction](https://mlsanity.com/paper/2112.07178/) (2021)
- [Hardware Security for and beyond CMOS Technology](https://mlsanity.com/paper/2001.08780/) (2020)
- [Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA](https://mlsanity.com/paper/2001.09672/) (2020)
- [LUT-Lock: A Novel LUT-based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection](https://mlsanity.com/paper/1804.11275/) (2018)
- [Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks](https://mlsanity.com/paper/2107.08695/) (2021)
- [TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits](https://mlsanity.com/paper/1505.02211/) (2015)
- [Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations](https://mlsanity.com/paper/1910.00737/) (2019)
- [Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration](https://mlsanity.com/paper/2112.02972/) (2021)
- [A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts](https://mlsanity.com/paper/2208.09235/) (2022)
- [Security Closure of IC Layouts Against Hardware Trojans](https://mlsanity.com/paper/2211.07997/) (2022)
- [Resynthesis-based Attacks Against Logic Locking](https://mlsanity.com/paper/2301.04400/) (2023)
- [SCARF: Securing Chips with a Robust Framework against Fabrication-time Hardware Trojans](https://mlsanity.com/paper/2402.12162/) (2024)

## Abstract (arXiv)

Due to cost benefits, supply chains of integrated circuits (ICs) are largely outsourced nowadays. However, passing ICs through various third-party providers gives rise to many security threats, like piracy of IC intellectual property or insertion of hardware Trojans, i.e., malicious circuit modifications. In this work, we proactively and systematically protect the physical layouts of ICs against post-design insertion of Trojans. Toward that end, we propose TroLLoc, a novel scheme for IC security closure that employs, for the first time, logic locking and layout hardening in unison. TroLLoc is fully integrated into a commercial-grade design flow, and TroLLoc is shown to be effective, efficient, and robust. Our work provides in-depth layout and security analysis considering the challenging benchmarks of the ISPD'22/23 contests for security closure. We show that TroLLoc successfully renders layouts resilient, with reasonable overheads, against (i) general prospects for Trojan insertion as in the ISPD'22 contest, (ii) actual Trojan insertion as in the ISPD'23 contest, and (iii) potential second-order attacks where adversaries would first (i.e., before Trojan insertion) try to bypass the locking defense, e.g., using advanced machine learning attacks. Finally, we release all our artifacts for independent verification [2].