# A Fully-Configurable Open-Source Software-Defined Digital Quantized Spiking Neural Core Architecture

arXiv: https://arxiv.org/abs/2404.02248 · HTML: https://mlsanity.com/paper/2404.02248/

## Key facts

- Cited by 8 papers in the map (data through 14 Oct 2026).
- Builds on 11 of its 37 references that are in the map.
- First posted on arXiv 2 Apr 2024.

## Builds on (most cited first, 11 of 11)

- [Understanding the Effective Receptive Field in Deep Convolutional Neural Networks](https://mlsanity.com/paper/1701.04128/) (2017)
- [Training Spiking Neural Networks Using Lessons From Deep Learning](https://mlsanity.com/paper/2109.12894/) (2021)
- [SpikingJelly: An open-source machine learning infrastructure platform for spike-based intelligence](https://mlsanity.com/paper/2310.16620/) (2023)
- [The Heidelberg spiking datasets for the systematic evaluation of spiking neural networks](https://mlsanity.com/paper/1910.07407/) (2019)
- [Learning Delays in Spiking Neural Networks using Dilated Convolutions with Learnable Spacings](https://mlsanity.com/paper/2306.17670/) (2023)
- [Comparing SNNs and RNNs on Neuromorphic Vision Datasets: Similarities and Differences](https://mlsanity.com/paper/2005.02183/) (2020)
- [Spiker: an FPGA-optimized Hardware acceleration for Spiking Neural Networks](https://mlsanity.com/paper/2201.06993/) (2022)
- [Why do networks have inhibitory/negative connections?](https://mlsanity.com/paper/2208.03211/) (2022)
- [evt_MNIST: A spike based version of traditional MNIST](https://mlsanity.com/paper/1604.06751/) (2016)
- [Real-Time Scheduling of Machine Learning Operations on Heterogeneous Neuromorphic SoC](https://mlsanity.com/paper/2209.14777/) (2022)
- [hxtorch.snn: Machine-learning-inspired Spiking Neural Network Modeling on BrainScaleS-2](https://mlsanity.com/paper/2212.12210/) (2022)

## Built on by (most cited first, 8 of 8)

- [Improving Performance of Spike-based Deep Q-Learning using Ternary Neurons](https://mlsanity.com/paper/2506.03392/) (2025)
- [Hardware-accelerated graph neural networks: an alternative approach for neuromorphic event-based audio classification and keyword spotting on SoC FPGA](https://mlsanity.com/paper/2602.16442/) (2026)
- [Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA](https://mlsanity.com/paper/2503.06629/) (2025)
- [Spiking Neural Network inference on FPGAs with hls4ml](https://mlsanity.com/paper/2606.10008/) (2026)
- [Efficient Aspect Term Extraction using Spiking Neural Network](https://mlsanity.com/paper/2601.06637/) (2026)
- [End-to-End Keyword Spotting on FPGA Using Graph Neural Networks with a Neuromorphic Auditory Sensor](https://mlsanity.com/paper/2605.09570/) (2026)
- [Scalable neuromorphic computing from autonomous spiking dynamics in a clockless reconfigurable chip](https://mlsanity.com/paper/2605.16114/) (2026)
- [Syn2Logic: End-to-End Neuromorphic Design Automation](https://mlsanity.com/paper/2608.25536/) (2026)

## Abstract (arXiv)

We introduce QUANTISENC, a fully configurable open-source software-defined digital quantized spiking neural core architecture to advance research in neuromorphic computing. QUANTISENC is designed hierarchically using a bottom-up methodology with multiple neurons in each layer and multiple layers in each core. The number of layers and neurons per layer can be configured via software in a top-down methodology to generate the hardware for a target spiking neural network (SNN) model. QUANTISENC uses leaky integrate and fire neurons (LIF) and current-based excitatory and inhibitory synapses (CUBA). The nonlinear dynamics of a neuron can be configured at run-time via programming its internal control registers. Each neuron performs signed fixed-point arithmetic with user-defined quantization and decimal precision. QUANTISENC supports all-to-all, one-to-one, and Gaussian connections between layers. Its hardware-software interface is integrated with a PyTorch-based SNN simulator. This integration allows to define and train an SNN model in PyTorch and evaluate the hardware performance (e.g., area, power, latency, and throughput) through FPGA prototyping and ASIC design. The hardware-software interface also takes advantage of the layer-based architecture and distributed memory organization of QUANTISENC to enable pipelining by overlapping computations on streaming data. Overall, the proposed software-defined hardware design methodology offers flexibility similar to that of high-level synthesis (HLS), but provides better hardware performance with zero hardware development effort. We evaluate QUANTISENC using three spiking datasets and show its superior performance against state-of the-art designs.