# Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving

arXiv: https://arxiv.org/abs/2403.19446 · HTML: https://mlsanity.com/paper/2403.19446/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 28 Mar 2024.

## Built on by (most cited first, 4 of 4)

- [DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale](https://mlsanity.com/paper/2502.01681/) (2025)
- [DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning](https://mlsanity.com/paper/2502.06816/) (2025)
- [Circuit-Aware SAT Solving: Guiding CDCL via Conditional Probabilities](https://mlsanity.com/paper/2508.04235/) (2025)
- [Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits](https://mlsanity.com/paper/2608.28188/) (2026)

## Abstract (arXiv)

The Circuit Satisfiability (CSAT) problem, a variant of the Boolean Satisfiability (SAT) problem, plays a critical role in integrated circuit design and verification. However, existing SAT solvers, optimized for Conjunctive Normal Form (CNF), often struggle with the intrinsic complexity of circuit structures when directly applied to CSAT instances. To address this challenge, we propose a novel preprocessing framework that leverages advanced logic synthesis techniques and a reinforcement learning (RL) agent to optimize CSAT problem instances. The framework introduces a cost-customized Look-Up Table (LUT) mapping strategy that prioritizes solving efficiency, effectively transforming circuits into simplified forms tailored for SAT solvers. Our method achieves significant runtime reductions across diverse industrial-scale CSAT benchmarks, seamlessly integrating with state-of-the-art SAT solvers. Extensive experimental evaluations demonstrate up to 63% reduction in solving time compared to conventional approaches, highlighting the potential of EDA-driven innovations to advance SAT-solving capabilities.