# E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis

arXiv: https://arxiv.org/abs/2403.14242 · HTML: https://mlsanity.com/paper/2403.14242/

## Key facts

- Cited by 7 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 21 Mar 2024.

## Built on by (most cited first, 7 of 7)

- [Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement](https://mlsanity.com/paper/2604.14989/) (2026)
- [e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving](https://mlsanity.com/paper/2508.13020/) (2025)
- [SkyEgg: Heterogeneity-Aware Hardware Synthesis via Equality Saturation](https://mlsanity.com/paper/2511.15323/) (2025)
- [PrefixAgent: An LLM-Powered Design Framework for Efficient Prefix Adder Optimization](https://mlsanity.com/paper/2507.06127/) (2025)
- [Revisit Choice Network for Synthesis and Technology Mapping](https://mlsanity.com/paper/2508.14068/) (2025)
- [GauS: Differentiable Scheduling Optimization via Gaussian Reparameterization](https://mlsanity.com/paper/2602.20427/) (2026)
- [TicTacBench: Benchmarking Timing Closure Capabilities of Coding Agents](https://mlsanity.com/paper/2609.23363/) (2026)

## Abstract (arXiv)

Logic synthesis plays a crucial role in the digital design flow. It has a decisive influence on the final Quality of Results (QoR) of the circuit implementations. However, existing multi-level logic optimization algorithms often employ greedy approaches with a series of local optimization steps. Each step breaks the circuit into small pieces (e.g., k-feasible cuts) and applies incremental changes to individual pieces separately. These local optimization steps could limit the exploration space and may miss opportunities for significant improvements. To address the limitation, this paper proposes using e-graph in logic synthesis. The new workflow, named Esyn, makes use of the well-established e-graph infrastructure to efficiently perform logic rewriting. It explores a diverse set of equivalent Boolean representations while allowing technology-aware cost functions to better support delay-oriented and area-oriented logic synthesis. Experiments over a wide range of benchmark designs show our proposed logic optimization approach reaches a wider design space compared to the commonly used AIG-based logic synthesis flow. It achieves on average 15.29% delay saving in delay-oriented synthesis and 6.42% area saving for area-oriented synthesis.