# Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators

arXiv: https://arxiv.org/abs/2403.04189 · HTML: https://mlsanity.com/paper/2403.04189/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 8 of its 21 references that are in the map.
- First posted on arXiv 7 Mar 2024.

## Builds on (most cited first, 8 of 8)

- [CrossLight: A Cross-Layer Optimized Silicon Photonic Neural Network Accelerator](https://mlsanity.com/paper/2102.06960/) (2021)
- [A Survey on Silicon Photonics for Deep Learning](https://mlsanity.com/paper/2101.01751/) (2021)
- [RecLight: A Recurrent Neural Network Accelerator with Integrated Silicon Photonics](https://mlsanity.com/paper/2209.00084/) (2022)
- [TRON: Transformer Neural Network Acceleration with Non-Coherent Silicon Photonics](https://mlsanity.com/paper/2303.12914/) (2023)
- [GHOST: A Graph Neural Network Accelerator using Silicon Photonics](https://mlsanity.com/paper/2307.01782/) (2023)
- [Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics](https://mlsanity.com/paper/2301.12252/) (2023)
- [ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication](https://mlsanity.com/paper/2208.04231/) (2022)
- [DeFT: A Deadlock-Free and Fault-Tolerant Routing Algorithm for 2.5D Chiplet Networks](https://mlsanity.com/paper/2112.09234/) (2021)

## Built on by (most cited first, 1 of 1)

- [SafeLight: Enhancing Security in Optical Convolutional Neural Network Accelerators](https://mlsanity.com/paper/2411.16712/) (2024)

## Abstract (arXiv)

Modern machine learning (ML) applications are becoming increasingly complex and monolithic (single chip) accelerator architectures cannot keep up with their energy efficiency and throughput demands. Even though modern digital electronic accelerators are gradually adopting 2.5D architectures with multiple smaller chiplets to improve scalability, they face fundamental limitations due to a reliance on slow metallic interconnects. This paper outlines how optical communication and computation can be leveraged in 2.5D platforms to realize energy-efficient and high throughput 2.5D ML accelerator architectures.