# Using the Abstract Computer Architecture Description Language to Model AI Hardware Accelerators

arXiv: https://arxiv.org/abs/2402.00069 · HTML: https://mlsanity.com/paper/2402.00069/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 8 of its 29 references that are in the map.
- First posted on arXiv 30 Jan 2024.

## Builds on (most cited first, 8 of 8)

- [PyTorch: An Imperative Style, High-Performance Deep Learning Library](https://mlsanity.com/paper/1912.01703/) (2019)
- [Hardware/Software Co-Exploration of Neural Architectures](https://mlsanity.com/paper/1907.04650/) (2019)
- [Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator](https://mlsanity.com/paper/2002.05022/) (2020)
- [DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architectures](https://mlsanity.com/paper/2002.11270/) (2020)
- [Rethinking Co-design of Neural Architectures and Hardware Accelerators](https://mlsanity.com/paper/2102.08619/) (2021)
- [Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices](https://mlsanity.com/paper/2209.03807/) (2022)
- [Tuning and optimization for a variety of many-core architectures without changing a single line of implementation code using the Alpaka library](https://mlsanity.com/paper/1706.10086/) (2017)
- [HDPython: A High Level Python Based Object-Oriented HDL Framework](https://mlsanity.com/paper/2011.02626/) (2020)

## Built on by (most cited first, 1 of 1)

- [Automatic Generation of Fast and Accurate Performance Models for Deep Neural Network Accelerators](https://mlsanity.com/paper/2409.08595/) (2024)

## Abstract (arXiv)

Artificial Intelligence (AI) has witnessed remarkable growth, particularly through the proliferation of Deep Neural Networks (DNNs). These powerful models drive technological advancements across various domains. However, to harness their potential in real-world applications, specialized hardware accelerators are essential. This demand has sparked a market for parameterizable AI hardware accelerators offered by different vendors. Manufacturers of AI-integrated products face a critical challenge: selecting an accelerator that aligns with their product's performance requirements. The decision involves choosing the right hardware and configuring a suitable set of parameters. However, comparing different accelerator design alternatives remains a complex task. Often, engineers rely on data sheets, spreadsheet calculations, or slow black-box simulators, which only offer a coarse understanding of the performance characteristics. The Abstract Computer Architecture Description Language (ACADL) is a concise formalization of computer architecture block diagrams, which helps to communicate computer architecture on different abstraction levels and allows for inferring performance characteristics. In this paper, we demonstrate how to use the ACADL to model AI hardware accelerators, use their ACADL description to map DNNs onto them, and explain the timing simulation semantics to gather performance results.