# Bayesian Inference Accelerator for Spiking Neural Networks

arXiv: https://arxiv.org/abs/2401.15453 · HTML: https://mlsanity.com/paper/2401.15453/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 27 Jan 2024.

## Built on by (most cited first, 2 of 2)

- [Temporal-Guided Spiking Neural Networks for Event-Based Human Action Recognition](https://mlsanity.com/paper/2503.17132/) (2025)
- [Bayes2IMC: In-Memory Computing for Bayesian Binary Neural Networks](https://mlsanity.com/paper/2411.07902/) (2024)

## Abstract (arXiv)

Bayesian neural networks offer better estimates of model uncertainty compared to frequentist networks. However, inference involving Bayesian models requires multiple instantiations or sampling of the network parameters, requiring significant computational resources. Compared to traditional deep learning networks, spiking neural networks (SNNs) have the potential to reduce computational area and power, thanks to their event-driven and spike-based computational framework. Most works in literature either address frequentist SNN models or non-spiking Bayesian neural networks. In this work, we demonstrate an optimization framework for developing and implementing efficient Bayesian SNNs in hardware by additionally restricting network weights to be binary-valued to further decrease power and area consumption. We demonstrate accuracies comparable to Bayesian binary networks with full-precision Bernoulli parameters, while requiring up to 25× less spikes than equivalent binary SNN implementations. We show the feasibility of the design by mapping it onto Zynq-7000, a lightweight SoC, and achieve a 6.5 × improvement in GOPS/DSP while utilizing up to 30 times less power compared to the state-of-the-art.