# Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators

arXiv: https://arxiv.org/abs/2401.09509 · HTML: https://mlsanity.com/paper/2401.09509/

## Key facts

- Cited by 9 papers in the map (data through 14 Oct 2026).
- Builds on 13 of its 31 references that are in the map.
- First posted on arXiv 17 Jan 2024.

## Builds on (most cited first, 13 of 13)

- [A Survey of Quantization Methods for Efficient Neural Network Inference](https://mlsanity.com/paper/2103.13630/) (2021)
- [FINN: A Framework for Fast, Scalable Binarized Neural Network Inference](https://mlsanity.com/paper/1612.07119/) (2016)
- [FT-ClipAct: Resilience Analysis of Deep Neural Networks and Improving their Fault Tolerance using Clipped Activation](https://mlsanity.com/paper/1912.00941/) (2019)
- [Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions](https://mlsanity.com/paper/1803.05900/) (2018)
- [A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks](https://mlsanity.com/paper/2305.05750/) (2023)
- [Accelerating CNN inference on FPGAs: A Survey](https://mlsanity.com/paper/1806.01683/) (2018)
- [DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators](https://mlsanity.com/paper/2303.08226/) (2023)
- [Exploring Fault-Energy Trade-offs in Approximate DNN Hardware Accelerators](https://mlsanity.com/paper/2101.02860/) (2021)
- [APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors](https://mlsanity.com/paper/2305.19733/) (2023)
- [Special Session: Approximation and Fault Resiliency of DNN Accelerators](https://mlsanity.com/paper/2306.04645/) (2023)
- [CNN2Gate: Toward Designing a General Framework for Implementation of Convolutional Neural Networks on FPGA](https://mlsanity.com/paper/2004.04641/) (2020)
- [Noise-Tolerance GPU-based Age Estimation Using ResNet-50](https://mlsanity.com/paper/2305.00848/) (2023)
- [A Novel Fault-Tolerant Logic Style with Self-Checking Capability](https://mlsanity.com/paper/2306.00844/) (2023)

## Built on by (most cited first, 9 of 9)

- [SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators](https://mlsanity.com/paper/2403.02946/) (2024)
- [Designing DNNs for a trade-off between robustness and processing performance in embedded devices](https://mlsanity.com/paper/2412.03682/) (2024)
- [AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators](https://mlsanity.com/paper/2403.02936/) (2024)
- [DoCIA: An Online Document-Level Context Incorporation Agent for Speech Translation](https://mlsanity.com/paper/2504.05122/) (2025)
- [HAWX: A Hardware-Aware FrameWork for Fast and Scalable ApproXimation of DNNs](https://mlsanity.com/paper/2602.16336/) (2026)
- [Mix-and-Match Pruning: Globally Guided Layer-Wise Sparsification of DNNs](https://mlsanity.com/paper/2603.20280/) (2026)
- [PhD Thesis Summary: Methods for Reliability Assessment and Enhancement of Deep Neural Network Hardware Accelerators](https://mlsanity.com/paper/2603.08724/) (2026)
- [Adaptive Soft Error Protection for Neural Network Processing](https://mlsanity.com/paper/2407.19664/) (2024)
- [REQAP: Resilient Weight Packing and Quantization for Edge DNN Acceleration](https://mlsanity.com/paper/2609.17555/) (2026)

## Abstract (arXiv)

The stringent requirements for the Deep Neural Networks (DNNs) accelerator's reliability stand along with the need for reducing the computational burden on the hardware platforms, i.e. reducing the energy consumption and execution time as well as increasing the efficiency of DNN accelerators. Moreover, the growing demand for specialized DNN accelerators with tailored requirements, particularly for safety-critical applications, necessitates a comprehensive design space exploration to enable the development of efficient and robust accelerators that meet those requirements. Therefore, the trade-off between hardware performance, i.e. area and delay, and the reliability of the DNN accelerator implementation becomes critical and requires tools for analysis. This paper presents a comprehensive methodology for exploring and enabling a holistic assessment of the trilateral impact of quantization on model accuracy, activation fault reliability, and hardware efficiency. A fully automated framework is introduced that is capable of applying various quantization-aware techniques, fault injection, and hardware implementation, thus enabling the measurement of hardware parameters. Moreover, this paper proposes a novel lightweight protection technique integrated within the framework to ensure the dependable deployment of the final systolic-array-based FPGA implementation. The experiments on established benchmarks demonstrate the analysis flow and the profound implications of quantization on reliability, hardware performance, and network accuracy, particularly concerning the transient faults in the network's activations.