# Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge

arXiv: https://arxiv.org/abs/2401.01141 · HTML: https://mlsanity.com/paper/2401.01141/

## Key facts

- Cited by 18 papers in the map (data through 14 Oct 2026).
- Builds on 13 of its 51 references that are in the map.
- First posted on arXiv 2 Jan 2024.

## Builds on (most cited first, 13 of 13)

- [Surrogate Gradient Learning in Spiking Neural Networks](https://mlsanity.com/paper/1901.09948/) (2019)
- [SpikingJelly: An open-source machine learning infrastructure platform for spike-based intelligence](https://mlsanity.com/paper/2310.16620/) (2023)
- [Accurate and efficient time-domain classification with adaptive spiking recurrent neural networks](https://mlsanity.com/paper/2103.12593/) (2021)
- [The BrainScaleS-2 accelerated neuromorphic system with hybrid plasticity](https://mlsanity.com/paper/2201.11063/) (2022)
- [ReckOn: A 28nm Sub-mm2 Task-Agnostic Spiking Recurrent Neural Network Processor Enabling On-Chip Learning over Second-Long Timescales](https://mlsanity.com/paper/2208.09759/) (2022)
- [Spiking Neural Network Integrated Circuits: A Review of Trends and Future Directions](https://mlsanity.com/paper/2203.07006/) (2022)
- [DYNAP-SE2: a scalable multi-core dynamic neuromorphic asynchronous spiking neural network processor](https://mlsanity.com/paper/2310.00564/) (2023)
- [FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks with Efficient DSP and Memory Optimization](https://mlsanity.com/paper/2301.01905/) (2023)
- [E3NE: An End-to-End Framework for Accelerating Spiking Neural Networks with Emerging Neural Encoding on FPGAs](https://mlsanity.com/paper/2111.10027/) (2021)
- [Spiker: an FPGA-optimized Hardware acceleration for Spiking Neural Networks](https://mlsanity.com/paper/2201.06993/) (2022)
- [Design Space Exploration of Hardware Spiking Neurons for Embedded Artificial Intelligence](https://mlsanity.com/paper/1910.01010/) (2019)
- [FPGA Implementation of Simplified Spiking Neural Network](https://mlsanity.com/paper/2010.01200/) (2020)
- [Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies](https://mlsanity.com/paper/2305.01818/) (2023)

## Built on by (most cited first, 18 of 18)

- [FTBC: Forward Temporal Bias Correction for Optimizing ANN-SNN Conversion](https://mlsanity.com/paper/2403.18388/) (2024)
- [Efficient FPGA-accelerated Convolutional Neural Networks for Cloud Detection on CubeSats](https://mlsanity.com/paper/2504.03891/) (2025)
- [SpikeExplorer: hardware-oriented Design Space Exploration for Spiking Neural Networks on FPGA](https://mlsanity.com/paper/2404.03714/) (2024)
- [Embedded event based object detection with spiking neural network](https://mlsanity.com/paper/2406.17617/) (2024)
- [Energy-Efficient Digital Design: A Comparative Study of Event-Driven and Clock-Driven Spiking Neurons](https://mlsanity.com/paper/2506.13268/) (2025)
- [SFATTI: Spiking FPGA Accelerator for Temporal Task-driven Inference -- A Case Study on MNIST](https://mlsanity.com/paper/2507.10561/) (2025)
- [Edge Intelligence with Spiking Neural Networks](https://mlsanity.com/paper/2507.14069/) (2025)
- [Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA](https://mlsanity.com/paper/2503.06629/) (2025)
- [Spiking Neural Network inference on FPGAs with hls4ml](https://mlsanity.com/paper/2606.10008/) (2026)
- [FeNN-DMA: A RISC-V SoC for SNN acceleration](https://mlsanity.com/paper/2511.00732/) (2025)
- [End-to-End Keyword Spotting on FPGA Using Graph Neural Networks with a Neuromorphic Auditory Sensor](https://mlsanity.com/paper/2605.09570/) (2026)
- [Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA](https://mlsanity.com/paper/2605.12217/) (2026)
- [Elastic Spiking Transformers for Efficient Gesture Understanding](https://mlsanity.com/paper/2605.13869/) (2026)
- [NeuroTrain: Surveying Local Learning Rules for Spiking Neural Networks with an Open Benchmarking Framework](https://mlsanity.com/paper/2605.15058/) (2026)
- [Scalable neuromorphic computing from autonomous spiking dynamics in a clockless reconfigurable chip](https://mlsanity.com/paper/2605.16114/) (2026)
- [Spiker-LL: An Energy-Efficient FPGA Accelerator Enabling Adaptive Local Learning in Spiking Neural Networks](https://mlsanity.com/paper/2605.18003/) (2026)
- [VQ4SNN: Vector Quantization for Memory-Efficient FPGA Spiking Neural Networks](https://mlsanity.com/paper/2606.20675/) (2026)
- [Syn2Logic: End-to-End Neuromorphic Design Automation](https://mlsanity.com/paper/2608.25536/) (2026)

## Abstract (arXiv)

Including Artificial Neural Networks in embedded systems at the edge allows applications to exploit Artificial Intelligence capabilities directly within devices operating at the network periphery. This paper introduces Spiker+, a comprehensive framework for generating efficient, low-power, and low-area customized Spiking Neural Networks (SNN) accelerators on FPGA for inference at the edge. Spiker+ presents a configurable multi-layer hardware SNN, a library of highly efficient neuron architectures, and a design framework, enabling the development of complex neural network accelerators with few lines of Python code. Spiker+ is tested on two benchmark datasets, the MNIST and the Spiking Heidelberg Digits (SHD). On the MNIST, it demonstrates competitive performance compared to state-of-the-art SNN accelerators. It outperforms them in terms of resource allocation, with a requirement of 7,612 logic cells and 18 Block RAMs (BRAMs), which makes it fit in very small FPGA, and power consumption, draining only 180mW for a complete inference on an input image. The latency is comparable to the ones observed in the state-of-the-art, with 780us/img. To the authors' knowledge, Spiker+ is the first SNN accelerator tested on the SHD. In this case, the accelerator requires 18,268 logic cells and 51 BRAM, with an overall power consumption of 430mW and a latency of 54 us for a complete inference on input data. This underscores the significance of Spiker+ in the hardware-accelerated SNN landscape, making it an excellent solution to deploy configurable and tunable SNN architectures in resource and power-constrained edge applications.