# Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits

arXiv: https://arxiv.org/abs/2312.14405 · HTML: https://mlsanity.com/paper/2312.14405/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- Builds on 12 of its 37 references that are in the map.
- First posted on arXiv 22 Dec 2023.

## Builds on (most cited first, 12 of 12)

- [Attention Is All You Need](https://mlsanity.com/paper/1706.03762/) (2017)
- [Deep Residual Learning for Image Recognition](https://mlsanity.com/paper/1512.03385/) (2015)
- [Adam: A Method for Stochastic Optimization](https://mlsanity.com/paper/1412.6980/) (2014)
- [Semi-Supervised Classification with Graph Convolutional Networks](https://mlsanity.com/paper/1609.02907/) (2016)
- [Graph Attention Networks](https://mlsanity.com/paper/1710.10903/) (2017)
- [Inductive Representation Learning on Large Graphs](https://mlsanity.com/paper/1706.02216/) (2017)
- [Layer Normalization](https://mlsanity.com/paper/1607.06450/) (2016)
- [GraphVAE: Towards Generation of Small Graphs Using Variational Autoencoders](https://mlsanity.com/paper/1802.03480/) (2018)
- [Global Self-Attention as a Replacement for Graph Convolution](https://mlsanity.com/paper/2108.03348/) (2021)
- [Pretraining Graph Neural Networks for few-shot Analog Circuit Modeling and Design](https://mlsanity.com/paper/2203.15913/) (2022)
- [A general approach for identifying hierarchical symmetry constraints for analog circuit layout](https://mlsanity.com/paper/2010.00051/) (2020)
- [TAG: Learning Circuit Spatial Embedding From Layouts](https://mlsanity.com/paper/2209.03465/) (2022)

## Built on by (most cited first, 3 of 3)

- [DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining](https://mlsanity.com/paper/2502.08949/) (2025)
- [Circuit Diagram Retrieval Based on Hierarchical Circuit Graph Representation](https://mlsanity.com/paper/2503.11658/) (2025)
- [Graph Neural Networks Based Analog Circuit Link Prediction](https://mlsanity.com/paper/2504.10240/) (2025)

## Abstract (arXiv)

In recent years, analog circuits have received extensive attention and are widely used in many emerging applications. The high demand for analog circuits necessitates shorter circuit design cycles. To achieve the desired performance and specifications, various geometrical symmetry constraints must be carefully considered during the analog layout process. However, the manual labeling of these constraints by experienced analog engineers is a laborious and time-consuming process. To handle the costly runtime issue, we propose a graph-based learning framework to automatically extract symmetric constraints in analog circuit layout. The proposed framework leverages the connection characteristics of circuits and the devices' information to learn the general rules of symmetric constraints, which effectively facilitates the extraction of device-level constraints on circuit netlists. The experimental results demonstrate that compared to state-of-the-art symmetric constraint detection approaches, our framework achieves higher accuracy and F1-score.