# Efficient and Scalable Architecture for Multiple-chip Implementation of Simulated Bifurcation Machines

arXiv: https://arxiv.org/abs/2311.17370 · HTML: https://mlsanity.com/paper/2311.17370/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 29 Nov 2023.

## Built on by (most cited first, 4 of 4)

- [Solving QUBO on the Loihi 2 Neuromorphic Processor](https://mlsanity.com/paper/2408.03076/) (2024)
- [Enhancing In-vehicle Multiple Object Tracking Systems with Embeddable Ising Machines](https://mlsanity.com/paper/2410.14093/) (2024)
- [Real-Time Black-Box Optimization for Dynamic Discrete Environments Using Embedded Ising Machines](https://mlsanity.com/paper/2506.16924/) (2025)
- [Machine Learning-assisted High-speed Combinatorial Optimization with Ising Machines for Dynamically Changing Problems](https://mlsanity.com/paper/2503.23966/) (2025)

## Abstract (arXiv)

Ising machines are specialized computers for finding the lowest energy states of Ising spin models, onto which many practical combinatorial optimization problems can be mapped. Simulated bifurcation (SB) is a quantum-inspired parallelizable algorithm for Ising problems that enables scalable multi-chip implementations of Ising machines. However, the computational performance of a previously proposed multi-chip architecture tends to saturate as the number of chips increases for a given problem size because both computation and communication are exclusive in the time domain. In this paper, we propose a streaming architecture for multi-chip implementations of SB-based Ising machines with full spin-to-spin connectivity. The data flow in in-chip computation is harmonized with the data flow in inter-chip communication, enabling the computation and communication to overlap and the communication time to be hidden. Systematic experiments demonstrate linear strong scaling of performance up to the vicinity of the ideal communication limit determined only by the latency of chip-to-chip communication. Our eight-FPGA (field-programmable gate array) cluster can compute a 32,768-spin problem with a high pipeline efficiency of 97.9%. The performance of a 79-FPGA cluster for a 100,000-spin problem, projected using a theoretical performance model validated on smaller experimental clusters, is comparable to that of a state-of-the-art 100,000-spin optical Ising machine.