# Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets

arXiv: https://arxiv.org/abs/2311.16417 · HTML: https://mlsanity.com/paper/2311.16417/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 28 Nov 2023.

## Built on by (most cited first, 3 of 3)

- [Efficient Heterogeneous Large Language Model Decoding with Model-Attention Disaggregation](https://mlsanity.com/paper/2405.01814/) (2024)
- [VR-YOLO: Enhancing PCB Defect Detection with Viewpoint Robustness Based on YOLO](https://mlsanity.com/paper/2507.02963/) (2025)
- [LLM-Augmented Bayesian Optimization with Adaptive Policies for Chiplet Design Space Exploration](https://mlsanity.com/paper/2610.14612/) (2026)

## Abstract (arXiv)

Fast-evolving artificial intelligence (AI) algorithms such as large language models have been driving the ever-increasing computing demands in today's data centers. Heterogeneous computing with domain-specific architectures (DSAs) brings many opportunities when scaling up and scaling out the computing system. In particular, heterogeneous chiplet architecture is favored to keep scaling up and scaling out the system as well as to reduce the design complexity and the cost stemming from the traditional monolithic chip design. However, how to interconnect computing resources and orchestrate heterogeneous chiplets is the key to success. In this paper, we first discuss the diversity and evolving demands of different AI workloads. We discuss how chiplet brings better cost efficiency and shorter time to market. Then we discuss the challenges in establishing chiplet interface standards, packaging, and security issues. We further discuss the software programming challenges in chiplet systems.