# Enhancing Energy-efficiency by Solving the Throughput Bottleneck of LSTM Cells for Embedded FPGAs

arXiv: https://arxiv.org/abs/2310.16842 · HTML: https://mlsanity.com/paper/2310.16842/

## Key facts

- Cited by 6 papers in the map (data through 14 Oct 2026).
- Builds on 0 of its 13 references that are in the map.
- First posted on arXiv 4 Oct 2023.

## Built on by (most cited first, 6 of 6)

- [Integer-only Quantized Transformers for Embedded FPGA-based Time-series Forecasting in AIoT](https://mlsanity.com/paper/2407.11041/) (2024)
- [ElasticAI: Creating and Deploying Energy-Efficient Deep Learning Accelerator for Pervasive Computing](https://mlsanity.com/paper/2409.09044/) (2024)
- [Resource-aware Mixed-precision Quantization for Enhancing Deployability of Transformers for Time-series Forecasting on Embedded FPGAs](https://mlsanity.com/paper/2410.03294/) (2024)
- [An Automated Approach to Collecting and Labeling Time Series Data for Event Detection Using Elastic Node Hardware](https://mlsanity.com/paper/2407.11042/) (2024)
- [Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity](https://mlsanity.com/paper/2407.12027/) (2024)
- [On-device AI: Quantization-aware Training of Transformers in Time-Series](https://mlsanity.com/paper/2408.16495/) (2024)

## Abstract (arXiv)

To process sensor data in the Internet of Things(IoTs), embedded deep learning for 1-dimensional data is an important technique. In the past, CNNs were frequently used because they are simple to optimise for special embedded hardware such as FPGAs. This work proposes a novel LSTM cell optimisation aimed at energy-efficient inference on end devices. Using the traffic speed prediction as a case study, a vanilla LSTM model with the optimised LSTM cell achieves 17534 inferences per second while consuming only 3.8 μJ per inference on the FPGA XC7S15 from Spartan-7 family. It achieves at least 5.4× faster throughput and 1.37× more energy efficient than existing approaches.