# FireFly v2: Advancing Hardware Support for High-Performance Spiking Neural Network with a Spatiotemporal FPGA Accelerator

arXiv: https://arxiv.org/abs/2309.16158 · HTML: https://mlsanity.com/paper/2309.16158/

## Key facts

- Cited by 7 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 28 Sep 2023.

## Built on by (most cited first, 7 of 7)

- [Pushing up to the Limit of Memory Bandwidth and Capacity Utilization for Efficient LLM Decoding on Embedded FPGA](https://mlsanity.com/paper/2502.10659/) (2025)
- [FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration with Reconfigurable Spatial Architecture](https://mlsanity.com/paper/2408.15578/) (2024)
- [Spiking Neural Network inference on FPGAs with hls4ml](https://mlsanity.com/paper/2606.10008/) (2026)
- [FeNN-DMA: A RISC-V SoC for SNN acceleration](https://mlsanity.com/paper/2511.00732/) (2025)
- [VQ4SNN: Vector Quantization for Memory-Efficient FPGA Spiking Neural Networks](https://mlsanity.com/paper/2606.20675/) (2026)
- [Syn2Logic: End-to-End Neuromorphic Design Automation](https://mlsanity.com/paper/2608.25536/) (2026)
- [An FPGA-Based Spiking Neural Network for Spatiotemporal Pattern Learning and Classification](https://mlsanity.com/paper/2610.17463/) (2026)

## Abstract (arXiv)

Spiking Neural Networks (SNNs) are expected to be a promising alternative to Artificial Neural Networks (ANNs) due to their strong biological interpretability and high energy efficiency. Specialized SNN hardware offers clear advantages over general-purpose devices in terms of power and performance. However, there's still room to advance hardware support for state-of-the-art (SOTA) SNN algorithms and improve computation and memory efficiency. As a further step in supporting high-performance SNNs on specialized hardware, we introduce FireFly v2, an FPGA SNN accelerator that can address the issue of non-spike operation in current SOTA SNN algorithms, which presents an obstacle in the end-to-end deployment onto existing SNN hardware. To more effectively align with the SNN characteristics, we design a spatiotemporal dataflow that allows four dimensions of parallelism and eliminates the need for membrane potential storage, enabling on-the-fly spike processing and spike generation. To further improve hardware acceleration performance, we develop a high-performance spike computing engine as a backend based on a systolic array operating at 500-600MHz. To the best of our knowledge, FireFly v2 achieves the highest clock frequency among all FPGA-based implementations. Furthermore, it stands as the first SNN accelerator capable of supporting non-spike operations, which are commonly used in advanced SNN algorithms. FireFly v2 has doubled the throughput and DSP efficiency when compared to our previous version of FireFly and it exhibits 1.33 times the DSP efficiency and 1.42 times the power efficiency compared to the current most advanced FPGA accelerators.