# Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator

arXiv: https://arxiv.org/abs/2308.11030 · HTML: https://mlsanity.com/paper/2308.11030/

## Key facts

- Cited by 30 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 21 Aug 2023.

## Built on by (most cited first, 30 of 30)

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- [Pimba: A Processing-in-Memory Acceleration for Post-Transformer Large Language Model Serving](https://mlsanity.com/paper/2507.10178/) (2025)
- [Sparse Attention Remapping with Clustering for Efficient LLM Decoding on PIM](https://mlsanity.com/paper/2505.05772/) (2025)
- [NPU Design for Diffusion Language Model Inference](https://mlsanity.com/paper/2601.20706/) (2026)
- [A3D-MoE: Acceleration of Large Language Models with Mixture of Experts via 3D Heterogeneous Integration](https://mlsanity.com/paper/2507.19142/) (2025)
- [AQPIM: Breaking the PIM Capacity Wall for LLMs with In-Memory Activation Quantization](https://mlsanity.com/paper/2604.18137/) (2026)
- [PIFS-Rec: Process-In-Fabric-Switch for Large-Scale Recommendation System Inferences](https://mlsanity.com/paper/2409.16633/) (2024)
- [BitStopper: An Efficient Transformer Attention Accelerator via Stage-fusion and Early Termination](https://mlsanity.com/paper/2512.06457/) (2025)
- [LOCALUT: Harnessing Capacity-Computation Tradeoffs for LUT-Based Inference in DRAM-PIM](https://mlsanity.com/paper/2604.04523/) (2026)
- [DSTAR: Accelerating Diffusion Transformers via Spatial and Temporal Redundancy Reduction](https://mlsanity.com/paper/2607.15846/) (2026)
- [FuseFlow: A Fusion-Centric Compilation Framework for Sparse Deep Learning on Streaming Dataflow](https://mlsanity.com/paper/2511.04768/) (2025)
- [Streaming Tensor Programs: A Streaming Abstraction for Dynamic Parallelism](https://mlsanity.com/paper/2511.07776/) (2025)
- [DCC: Data-Centric Compilation of Machine Learning Kernels for Processing-In-Memory Architectures](https://mlsanity.com/paper/2511.15503/) (2025)
- [A Scheduling Framework for Efficient MoE Inference on Edge GPU-NDP Systems](https://mlsanity.com/paper/2601.03992/) (2026)
- [From Buffers to Registers: Unlocking Fine-Grained FlashAttention with Hybrid-Bonded 3D NPU Co-Design](https://mlsanity.com/paper/2602.11016/) (2026)
- [Hardware-Software Co-design for 3D-DRAM-based LLM Serving Accelerator](https://mlsanity.com/paper/2603.04797/) (2026)
- [ELMoE-3D: Leveraging Intrinsic Elasticity of MoE for Hybrid-Bonding-Enabled Self-Speculative Decoding in On-Premises Serving](https://mlsanity.com/paper/2604.14626/) (2026)
- [Sieve: Dynamic Expert-Aware PIM Acceleration for Evolving Mixture-of-Experts Models](https://mlsanity.com/paper/2605.11277/) (2026)
- [ORBIS: Output-Guided Token Reduction with Distribution-Aware Matching for Video Diffusion Acceleration](https://mlsanity.com/paper/2605.22015/) (2026)
- [Beyond Prefill-Decode Disaggregation: Dissecting LLM Inference for Heterogeneous Platforms via Dynamic Operator Scheduling](https://mlsanity.com/paper/2607.25498/) (2026)
- [APEX: Adaptive Expert Prefetching for Memory-Efficient Edge MoE Inference](https://mlsanity.com/paper/2608.11688/) (2026)
- [HYDRA: A Heterogeneous Chiplet DSE Framework for Serving Dynamic Hybrid LLM Workloads](https://mlsanity.com/paper/2608.19395/) (2026)
- [NOVA: Technology-Architecture Co-Design of Near-Memory Processing for Attention-SSM-MoE Hybrid LLM Inference](https://mlsanity.com/paper/2608.22613/) (2026)
- [FLINT: Efficiently Leveraging High Bandwidth Flash for Capacity-Scalable LLM Inference Acceleration](https://mlsanity.com/paper/2608.25062/) (2026)
- [FlexPosit: Tunable Fractional Precision for LLM Inference Accelerators](https://mlsanity.com/paper/2609.04724/) (2026)
- [SAGE: Semantic-Aware Geographic Error Recovery for AI Data Movement](https://mlsanity.com/paper/2609.10126/) (2026)
- [MiX: Micro-Inverted-Scaling for End-to-End Low-Bit Vision-Language Model Acceleration](https://mlsanity.com/paper/2609.19683/) (2026)

## Abstract (arXiv)

We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and DRAM to meet the increasing research effort in improving the performance, security, and reliability of memory systems. Ramulator 2.0 abstracts and models key components in a DRAM-based memory system and their interactions into shared interfaces and independent implementations. Doing so enables easy modification and extension of the modeled functions of the memory controller and DRAM in Ramulator 2.0. The DRAM specification syntax of Ramulator 2.0 is concise and human-readable, facilitating easy modifications and extensions. Ramulator 2.0 implements a library of reusable templated lambda functions to model the functionalities of DRAM commands to simplify the implementation of new DRAM standards, including DDR5, LPDDR5, HBM3, and GDDR6. We showcase Ramulator 2.0's modularity and extensibility by implementing and evaluating a wide variety of RowHammer mitigation techniques that require different memory controller design changes. These techniques are added modularly as separate implementations without changing any code in the baseline memory controller implementation. Ramulator 2.0 is rigorously validated and maintains a fast simulation speed compared to existing cycle-accurate DRAM simulators. Ramulator 2.0 is open-sourced under the permissive MIT license at https://github.com/CMU-SAFARI/ramulator2