# Constrained Bayesian Optimization Using a Lagrange Multiplier Applied to Power Transistor Design

arXiv: https://arxiv.org/abs/2308.09612 · HTML: https://mlsanity.com/paper/2308.09612/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 1 of its 48 references that are in the map.
- First posted on arXiv 18 Aug 2023.

## Builds on (most cited first, 1 of 1)

- [A Tutorial on Bayesian Optimization](https://mlsanity.com/paper/1807.02811/) (2018)

## Built on by (most cited first, 1 of 1)

- [Unified Audio Intelligence Without Regressing on Text Intelligence](https://mlsanity.com/paper/2607.05196/) (2026)

## Abstract (arXiv)

We propose a novel constrained Bayesian Optimization (BO) algorithm optimizing the design process of Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) transistors while realizing a target Breakdown Voltage (BV). We convert the constrained BO problem into a conventional BO problem using a Lagrange multiplier. Instead of directly optimizing the traditional Figure-of-Merit (FOM), we set the Lagrangian as the objective function of BO. This adaptive objective function with a changeable Lagrange multiplier can address constrained BO problems which have constraints that require costly evaluations, without the need for additional surrogate models to approximate constraints. Our algorithm enables a device designer to set the target BV in the design space, and obtain a device that satisfies the optimized FOM and the target BV constraint automatically. Utilizing this algorithm, we have also explored the physical limits of the FOM for our devices in 30 - 50 V range within the defined design space.