# iEDA: An Open-Source Intelligent Physical Implementation Toolkit and Library

arXiv: https://arxiv.org/abs/2308.01857 · HTML: https://mlsanity.com/paper/2308.01857/

## Key facts

- Cited by 7 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 3 Aug 2023.

## Built on by (most cited first, 7 of 7)

- [ChatEDA: A Large Language Model Powered Autonomous Agent for EDA](https://mlsanity.com/paper/2308.10204/) (2023)
- [Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA](https://mlsanity.com/paper/2407.15353/) (2024)
- [EDA Corpus: A Large Language Model Dataset for Enhanced Interaction with OpenROAD](https://mlsanity.com/paper/2405.06676/) (2024)
- [OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis](https://mlsanity.com/paper/2411.09422/) (2024)
- [IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA](https://mlsanity.com/paper/2407.12576/) (2024)
- [FluxEDA: A Unified Execution Infrastructure for Stateful Agentic EDA](https://mlsanity.com/paper/2603.25243/) (2026)
- [BoolSkeleton: Boolean Network Skeletonization via Homogeneous Pattern Reduction](https://mlsanity.com/paper/2511.02196/) (2025)

## Abstract (arXiv)

Open-source EDA shows promising potential in unleashing EDA innovation and lowering the cost of chip design. This paper presents an open-source EDA project, iEDA, aiming for building a basic infrastructure for EDA technology evolution and closing the industrial-academic gap in the EDA area. iEDA now covers the whole flow of physical design (including Floorplan, Placement, CTS, Routing, Timing Optimization etc.), and part of the analysis tools (Static Timing Analysis and Power Analysis). To demonstrate the effectiveness of iEDA, we implement and tape out three chips of different scales (from 700k to 1.5M gates) on different process nodes (110nm and 28nm) with iEDA. iEDA is publicly available from the project home page http://ieda.oscc.cc.