# Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection

arXiv: https://arxiv.org/abs/2306.08936 · HTML: https://mlsanity.com/paper/2306.08936/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 15 Jun 2023.

## Built on by (most cited first, 3 of 3)

- [Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits](https://mlsanity.com/paper/2507.06535/) (2025)
- [Few-shot Learning on AMS Circuits and Its Application to Parasitic Capacitance Prediction](https://mlsanity.com/paper/2507.06538/) (2025)
- [ParasGB: A Graph Benchmark Suite for Parasitic Estimation on AMS Circuits](https://mlsanity.com/paper/2607.23225/) (2026)

## Abstract (arXiv)

In energy-constrained scenarios such as IoT applications, the primary requirement for System-on-Chips (SoCs) is to increase battery life. However, when performing sub/near-threshold operations, the relatively large leakage current hinders Static Random Access Memory (SRAM) from normal read/write functionalities at the lowest possible voltage (VDDMIN). In this work, we propose an Ultra8T SRAM to aggressively reduce VDDMIN by using a leakage detection strategy where the safety sensing time on bitlines is quantified without any additional hardware overhead. We validate the proposed Ultra8T using a 256x64 array in 28nm CMOS technology. Post-simulations show successful read operation at 0.25V with 1.11μs read delay, and the minimum energy required is 1.69pJ at 0.4V.