# RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edge

arXiv: https://arxiv.org/abs/2306.06493 · HTML: https://mlsanity.com/paper/2306.06493/

## Key facts

- Cited by 11 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 10 Jun 2023.

## Built on by (most cited first, 11 of 11)

- [Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloads](https://mlsanity.com/paper/2412.11702/) (2024)
- [POLARON: Precision-aware On-device Learning and Adaptive Runtime-cONfigurable AI acceleration](https://mlsanity.com/paper/2506.08785/) (2025)
- [HYDRA: Hybrid Data Multiplexing and Run-time Layer Configurable DNN Accelerator](https://mlsanity.com/paper/2409.04976/) (2024)
- [HyperCam: Low-Power Onboard Computer Vision for IoT Cameras](https://mlsanity.com/paper/2501.10547/) (2025)
- [RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI](https://mlsanity.com/paper/2511.21232/) (2025)
- [CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applications](https://mlsanity.com/paper/2602.19268/) (2026)
- [Neural Signal Compression using RAMAN tinyML Accelerator for BCI Applications](https://mlsanity.com/paper/2504.06996/) (2025)
- [HOMI: Ultra-Fast EdgeAI platform for Event Cameras](https://mlsanity.com/paper/2508.12637/) (2025)
- [On-Device Continual Learning for Unsupervised Visual Anomaly Detection in Dynamic Manufacturing](https://mlsanity.com/paper/2512.13497/) (2025)
- [SHIELD8-UAV: Sequential 8-bit Hardware Implementation of a Precision-Aware 1D-F-CNN for Low-Energy UAV Acoustic Detection and Temporal Tracking](https://mlsanity.com/paper/2603.01069/) (2026)
- [Right In-Place (RiP) Convolution: A Simple, General, and Near-Optimal Strategy for Memory-Efficient CNN Inference](https://mlsanity.com/paper/2610.00586/) (2026)

## Abstract (arXiv)

Deep Neural Network (DNN) based inference at the edge is challenging as these compute and data-intensive algorithms need to be implemented at low cost and low power while meeting the latency constraints of the target applications. Sparsity, in both activations and weights inherent to DNNs, is a key knob to leverage. In this paper, we present RAMAN, a Re-configurable and spArse tinyML Accelerator for infereNce on edge, architected to exploit the sparsity to reduce area (storage), power as well as latency. RAMAN can be configured to support a wide range of DNN topologies - consisting of different convolution layer types and a range of layer parameters (feature-map size and the number of channels). RAMAN can also be configured to support accuracy vs power/latency tradeoffs using techniques deployed at compile-time and run-time. We present the salient features of the architecture, provide implementation results and compare the same with the state-of-the-art. RAMAN employs novel dataflow inspired by Gustavson's algorithm that has optimal input activation (IA) and output activation (OA) reuse to minimize memory access and the overall data movement cost. The dataflow allows RAMAN to locally reduce the partial sum (Psum) within a processing element array to eliminate the Psum writeback traffic. Additionally, we suggest a method to reduce peak activation memory by overlapping IA and OA on the same memory space, which can reduce storage requirements by up to 50%. RAMAN was implemented on a low-power and resource-constrained Efinix Ti60 FPGA with 37.2K LUTs and 8.6K register utilization. RAMAN processes all layers of the MobileNetV1 model at 98.47 GOp/s/W and the DS-CNN model at 79.68 GOp/s/W by leveraging both weight and activation sparsity.