# Mixed-TD: Efficient Neural Network Accelerator with Layer-Specific Tensor Decomposition

arXiv: https://arxiv.org/abs/2306.05021 · HTML: https://mlsanity.com/paper/2306.05021/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 12 of its 32 references that are in the map.
- First posted on arXiv 8 Jun 2023.

## Builds on (most cited first, 12 of 12)

- [RepVGG: Making VGG-style ConvNets Great Again](https://mlsanity.com/paper/2101.03697/) (2021)
- [Tensor Ring Decomposition](https://mlsanity.com/paper/1606.05535/) (2016)
- [BRP-NAS: Prediction-based NAS using GCNs](https://mlsanity.com/paper/2007.08668/) (2020)
- [TensorLy: Tensor Learning in Python](https://mlsanity.com/paper/1610.09555/) (2016)
- [ChamNet: Towards Efficient Network Design through Platform-Aware Model Adaptation](https://mlsanity.com/paper/1812.08934/) (2018)
- [Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions](https://mlsanity.com/paper/1803.05900/) (2018)
- [Memory-Efficient Dataflow Inference for Deep CNNs on FPGA](https://mlsanity.com/paper/2011.07317/) (2020)
- [HPIPE: Heterogeneous Layer-Pipelined and Sparse-Aware CNN Inference for FPGAs](https://mlsanity.com/paper/2007.10451/) (2020)
- [SAMO: Optimised Mapping of Convolutional Neural Networks to Streaming Architectures](https://mlsanity.com/paper/2112.00170/) (2021)
- [N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores](https://mlsanity.com/paper/2112.08193/) (2021)
- [Design of High-Throughput Mixed-Precision CNN Accelerators on FPGA](https://mlsanity.com/paper/2208.04854/) (2022)
- [SVD-NAS: Coupling Low-Rank Approximation and Neural Architecture Search](https://mlsanity.com/paper/2208.10404/) (2022)

## Abstract (arXiv)

Neural Network designs are quite diverse, from VGG-style to ResNet-style, and from Convolutional Neural Networks to Transformers. Towards the design of efficient accelerators, many works have adopted a dataflow-based, inter-layer pipelined architecture, with a customised hardware towards each layer, achieving ultra high throughput and low latency. The deployment of neural networks to such dataflow architecture accelerators is usually hindered by the available on-chip memory as it is desirable to preload the weights of neural networks on-chip to maximise the system performance. To address this, networks are usually compressed before the deployment through methods such as pruning, quantization and tensor decomposition. In this paper, a framework for mapping CNNs onto FPGAs based on a novel tensor decomposition method called Mixed-TD is proposed. The proposed method applies layer-specific Singular Value Decomposition (SVD) and Canonical Polyadic Decomposition (CPD) in a mixed manner, achieving 1.73x to 10.29x throughput per DSP to state-of-the-art CNNs. Our work is open-sourced: https://github.com/Yu-Zhewen/Mixed-TD