# A Novel Fault-Tolerant Logic Style with Self-Checking Capability

arXiv: https://arxiv.org/abs/2306.00844 · HTML: https://mlsanity.com/paper/2306.00844/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 2 of its 27 references that are in the map.
- First posted on arXiv 31 May 2023.

## Builds on (most cited first, 2 of 2)

- [Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices](https://mlsanity.com/paper/2008.08409/) (2020)
- [DMR-based Technique for Fault Tolerant AES S-box Architecture](https://mlsanity.com/paper/2009.05329/) (2020)

## Built on by (most cited first, 2 of 2)

- [Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators](https://mlsanity.com/paper/2401.09509/) (2024)
- [AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators](https://mlsanity.com/paper/2403.02936/) (2024)

## Abstract (arXiv)

We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for each rail of outputs enables construction of faulttolerant configurable circuits. The AND and OR gates consist of 8 transistors based on CNFET technology, while the proposed XOR gate benefits from both CNFET and low-power MGDI technologies in its transistor arrangement. To demonstrate the feasibility of our new logic gates, we used an AES S-box implementation as the use case. The extensive simulation results using HSPICE indicate that the case-study circuit using on proposed gates has superior speed and power consumption compared to other implementations with error-detection capability