# Towards Neural Path Tracing in SRAM

arXiv: https://arxiv.org/abs/2305.20061 · HTML: https://mlsanity.com/paper/2305.20061/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 31 May 2023.

## Built on by (most cited first, 2 of 2)

- [Radiant Foam Rendering on a Graph Processor](https://mlsanity.com/paper/2601.04382/) (2026)
- [Rendering 3D Gaussians on a Graph Processor](https://mlsanity.com/paper/2607.15951/) (2026)

## Abstract (arXiv)

We present an experimental neural path tracer designed to exploit the large on-chip memory of Graphcore intelligence-processing-units (IPUs). This open source renderer demonstrates how to map path tracing to the novel software and hardware architecture and is a useful tool for analysing in-cache neural-rendering scenarios. Such scenarios will be increasingly important if rasterisation is replaced by combinations of ray/path tracing, neural-radiance caching, and AI denoising/up-scaling, for which small neural networks are already routinely employed. A detailed description of the implementation also serves as a self-contained resource for more general software design on IPU.