# Hardware Acceleration for Open Radio Access Networks: A Contemporary Overview

arXiv: https://arxiv.org/abs/2305.09588 · HTML: https://mlsanity.com/paper/2305.09588/

## Key facts

- Cited by 4 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 16 May 2023.

## Built on by (most cited first, 4 of 4)

- [AI-RAN: Transforming RAN with AI-driven Computing Infrastructure](https://mlsanity.com/paper/2501.09007/) (2025)
- [Beyond Connectivity: An Open Architecture for AI-RAN Convergence in 6G](https://mlsanity.com/paper/2507.06911/) (2025)
- [Online Frequency Scheduling by Learning Parallel Actions](https://mlsanity.com/paper/2406.05041/) (2024)
- [AI-RAN on NPUs: Baseband Processing Without Baseband Chips](https://mlsanity.com/paper/2607.04224/) (2026)

## Abstract (arXiv)

Radio access networks (RAN) are going through a paradigm shift towards interoperable, intelligent, software-defined, and cloud-native open RAN solutions. A key challenge towards the adoption and deployment of open RAN at scale is performance. Hence, it is critical to leverage the power of hardware acceleration to offload compute-heavy RAN workloads to specialized hardware devices to enable accelerated compute for open RAN deployments. In this article, we provide a state-of-the-art overview of hardware acceleration for open RAN in the fifth generation (5G) wireless networks. We also present a practical implementation of inline hardware acceleration for open RAN layer 1 processing and identify several areas for future exploration towards the sixth generation (6G) wireless networks.