# Design optimization for high-performance computing using FPGA

arXiv: https://arxiv.org/abs/2304.12474 · HTML: https://mlsanity.com/paper/2304.12474/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 4 of its 24 references that are in the map.
- First posted on arXiv 24 Apr 2023.

## Builds on (most cited first, 4 of 4)

- [FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks](https://mlsanity.com/paper/1809.04570/) (2018)
- [Nengo and low-power AI hardware for robust, embedded neurorobotics](https://mlsanity.com/paper/2007.10227/) (2020)
- [An Energy-Efficient Reconfigurable Autoencoder Implementation on FPGA](https://mlsanity.com/paper/2301.07050/) (2023)
- [FPGA-Based In-Vivo Calcium Image Decoding for Closed-Loop Feedback Applications](https://mlsanity.com/paper/2212.04736/) (2022)

## Built on by (most cited first, 2 of 2)

- [Exploiting FPGA Capabilities for Accelerated Biomedical Computing](https://mlsanity.com/paper/2307.07914/) (2023)
- [Harnessing FPGA Technology for Enhanced Biomedical Computation](https://mlsanity.com/paper/2311.12439/) (2023)

## Abstract (arXiv)

Reconfigurable architectures like Field Programmable Gate Arrays (FPGAs) have been used for accelerating computations in several domains because of their unique combination of flexibility, performance, and power efficiency. However, FPGAs have not been widely used for high-performance computing, primarily because of their programming complexity and difficulties in optimizing performance. We optimize Tensil AI's open-source inference accelerator for maximum performance using ResNet20 trained on CIFAR in this paper in order to gain insight into the use of FPGAs for high-performance computing. In this paper, we show how improving hardware design, using Xilinx Ultra RAM, and using advanced compiler strategies can lead to improved inference performance. We also demonstrate that running the CIFAR test data set shows very little accuracy drop when rounding down from the original 32-bit floating point. The heterogeneous computing model in our platform allows us to achieve a frame rate of 293.58 frames per second (FPS) and a %90 accuracy on a ResNet20 trained using CIFAR. The experimental results show that the proposed accelerator achieves a throughput of 21.12 Giga-Operations Per Second (GOP/s) with a 5.21 W on-chip power consumption at 100 MHz. The comparison results with off-the-shelf devices and recent state-of-the-art implementations illustrate that the proposed accelerator has obvious advantages in terms of energy efficiency.