# Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks

arXiv: https://arxiv.org/abs/2304.11761 · HTML: https://mlsanity.com/paper/2304.11761/

## Key facts

- Cited by 11 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 23 Apr 2023.

## Built on by (most cited first, 11 of 11)

- [Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms](https://mlsanity.com/paper/2407.15026/) (2024)
- [DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators](https://mlsanity.com/paper/2404.13049/) (2024)
- [Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation](https://mlsanity.com/paper/2503.12946/) (2025)
- [FlowPlace: Flow Matching for Chip Placement](https://mlsanity.com/paper/2604.23658/) (2026)
- [MAGE: Human-Like Macro Placement via Agentic Multimodal Reasoning](https://mlsanity.com/paper/2607.18536/) (2026)
- [Re2MaP: Macro Placement by Recursively Prototyping and Packing Tree-based Relocating](https://mlsanity.com/paper/2511.08054/) (2025)
- [Architectural Design and Performance Analysis of FPGA based AI Accelerators: A Comprehensive Review](https://mlsanity.com/paper/2603.08740/) (2026)
- [How Can Reinforcement Learning Achieve Expert-level Placement?](https://mlsanity.com/paper/2604.25191/) (2026)
- [Agentic Electronic Design Automation: A Handoff Perspective](https://mlsanity.com/paper/2606.19795/) (2026)
- [PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization](https://mlsanity.com/paper/2608.13790/) (2026)
- [PlaceReasoner-Beta: Reasoning-Driven Macro Placement and Benchmarking](https://mlsanity.com/paper/2609.21263/) (2026)

## Abstract (arXiv)

In a typical RTL to GDSII flow, floorplanning or macro placement is a critical step in achieving decent quality of results (QoR). Moreover, in today's physical synthesis flows (e.g., Synopsys Fusion Compiler or Cadence Genus iSpatial), a floorplan .def with macro and IO pin placements is typically needed as an input to the front-end physical synthesis. Recently, with the increasing complexity of IP blocks, and in particular with auto-generated RTL for machine learning (ML) accelerators, the number of hard macros in a single RTL block can easily run into the several hundreds. This makes the task of generating an automatic floorplan (.def) with IO pin and macro placements for front-end physical synthesis even more critical and challenging. The so-called peripheral approach of forcing macros to the periphery of the layout is no longer viable when the ratio of the sum of the macro perimeters to the floorplan perimeter is large, since this increases the required stacking depth of macros. In this paper, we develop a novel multilevel physical planning approach that exploits the hierarchy and dataflow inherent in the design RTL, and describe its realization in a new hierarchical macro placer, Hier-RTLMP. Hier-RTLMP borrows from traditional approaches used in manual system-on-chip (SoC) floorplanning to create an automatic macro placement for use with large IP blocks containing very large numbers of hard macros. Empirical studies demonstrate substantial improvements over the previous RTL-MP macro placement approach, and promising post-route improvements relative to a leading commercial place-and-route tool.