# Information Flow Coverage Metrics for Hardware Security Verification

arXiv: https://arxiv.org/abs/2304.08263 · HTML: https://mlsanity.com/paper/2304.08263/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 12 Apr 2023.

## Built on by (most cited first, 1 of 1)

- [LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) Verification](https://mlsanity.com/paper/2601.02624/) (2026)

## Abstract (arXiv)

Security graphs model attacks, defenses, mitigations, and vulnerabilities on computer networks and systems. With proper attributes, they provide security metrics using standard graph algorithms. A hyperflow graph is a register-transfer level (RTL) hardware security graph that facilitates security verification. A hyperflow graph models information flows and is annotated with attributes that allow security metrics to measure flow paths, flow conditions, and flow rates. Hyperflow graphs enable the understanding of hardware vulnerabilities related to confidentiality, integrity, and availability, as shown on the OpenTitan hardware root of trust under several threat models.