# High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures

arXiv: https://arxiv.org/abs/2304.07608 · HTML: https://mlsanity.com/paper/2304.07608/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- Builds on 10 of its 34 references that are in the map.
- First posted on arXiv 15 Apr 2023.

## Builds on (most cited first, 10 of 10)

- [Photonics for artificial intelligence and neuromorphic computing](https://mlsanity.com/paper/2011.00111/) (2020)
- [Towards Mixed-Precision Quantization of Neural Networks via Constrained Optimization](https://mlsanity.com/paper/2110.06554/) (2021)
- [Digital Electronics and Analog Photonics for Convolutional Neural Networks (DEAP-CNNs)](https://mlsanity.com/paper/1907.01525/) (2019)
- [ROBIN: A Robust Optical Binary Neural Network Accelerator](https://mlsanity.com/paper/2107.05530/) (2021)
- [Photonic Reconfigurable Accelerators for Efficient Inference of CNNs with Mixed-Sized Tensors](https://mlsanity.com/paper/2207.05278/) (2022)
- [Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing](https://mlsanity.com/paper/2101.00557/) (2021)
- [SCONNA: A Stochastic Computing Based Optical Accelerator for Ultra-Fast, Energy-Efficient Inference of Integer-Quantized CNNs](https://mlsanity.com/paper/2302.07036/) (2023)
- [An Optical XNOR-Bitcount Based Accelerator for Efficient Inference of Binary Neural Networks](https://mlsanity.com/paper/2302.06405/) (2023)
- [PROTEUS: Rule-Based Self-Adaptation in Photonic NoCs for Loss-Aware Co-Management of Laser Power and Performance](https://mlsanity.com/paper/2008.07566/) (2020)
- [A Bit-Parallel Deterministic Stochastic Multiplier](https://mlsanity.com/paper/2302.08324/) (2023)

## Built on by (most cited first, 1 of 1)

- [ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks](https://mlsanity.com/paper/2407.12638/) (2024)

## Abstract (arXiv)

In this paper, we present microring resonator (MRR) based polymorphic E-O circuits and architectures that can be employed for high-speed and energy-efficient non-binary reconfigurable computing. Our polymorphic E-O circuits can be dynamically programmed to implement different logic and arithmetic functions at different times. They can provide compactness and polymorphism to consequently improve operand handling, reduce idle time, and increase amortization of area and static power overheads. When combined with flexible photodetectors with the innate ability to accumulate a high number of optical pulses in situ, our circuits can support energy-efficient processing of data in non-binary formats such as stochastic/unary and high-dimensional reservoir formats. Furthermore, our polymorphic E-O circuits enable configurable E-O computing accelerator architectures for processing binarized and integer quantized convolutional neural networks (CNNs). We compare our designed polymorphic E-O circuits and architectures to several circuits and architectures from prior works in terms of area, latency, and energy consumption.