# HARFLOW3D: A Latency-Oriented 3D-CNN Accelerator Toolflow for HAR on FPGA Devices

arXiv: https://arxiv.org/abs/2303.17218 · HTML: https://mlsanity.com/paper/2303.17218/

## Key facts

- Cited by 5 papers in the map (data through 14 Oct 2026).
- Builds on 6 of its 21 references that are in the map.
- First posted on arXiv 30 Mar 2023.

## Builds on (most cited first, 6 of 6)

- [SlowFast Networks for Video Recognition](https://mlsanity.com/paper/1812.03982/) (2018)
- [A Closer Look at Spatiotemporal Convolutions for Action Recognition](https://mlsanity.com/paper/1711.11248/) (2017)
- [X3D: Expanding Architectures for Efficient Video Recognition](https://mlsanity.com/paper/2004.04730/) (2020)
- [Can Spatiotemporal 3D CNNs Retrace the History of 2D CNNs and ImageNet?](https://mlsanity.com/paper/1711.09577/) (2017)
- [FINN: A Framework for Fast, Scalable Binarized Neural Network Inference](https://mlsanity.com/paper/1612.07119/) (2016)
- [Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions](https://mlsanity.com/paper/1803.05900/) (2018)

## Built on by (most cited first, 5 of 5)

- [SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devices](https://mlsanity.com/paper/2309.01587/) (2023)
- [FMM-X3D: FPGA-based modeling and mapping of X3D for Human Action Recognition](https://mlsanity.com/paper/2305.18479/) (2023)
- [fpgaHART: A toolflow for throughput-oriented acceleration of 3D CNNs for HAR onto FPGAs](https://mlsanity.com/paper/2305.19896/) (2023)
- [FPGA-based Acceleration for Convolutional Neural Networks: A Comprehensive Review](https://mlsanity.com/paper/2505.13461/) (2025)
- [SMOF: Streaming Modern CNNs on FPGAs with Smart Off-Chip Eviction](https://mlsanity.com/paper/2403.18921/) (2024)

## Abstract (arXiv)

For Human Action Recognition tasks (HAR), 3D Convolutional Neural Networks have proven to be highly effective, achieving state-of-the-art results. This study introduces a novel streaming architecture based toolflow for mapping such models onto FPGAs considering the model's inherent characteristics and the features of the targeted FPGA device. The HARFLOW3D toolflow takes as input a 3D CNN in ONNX format and a description of the FPGA characteristics, generating a design that minimizes the latency of the computation. The toolflow is comprised of a number of parts, including i) a 3D CNN parser, ii) a performance and resource model, iii) a scheduling algorithm for executing 3D models on the generated hardware, iv) a resource-aware optimization engine tailored for 3D models, v) an automated mapping to synthesizable code for FPGAs. The ability of the toolflow to support a broad range of models and devices is shown through a number of experiments on various 3D CNN and FPGA system pairs. Furthermore, the toolflow has produced high-performing results for 3D CNN models that have not been mapped to FPGAs before, demonstrating the potential of FPGA-based systems in this space. Overall, HARFLOW3D has demonstrated its ability to deliver competitive latency compared to a range of state-of-the-art hand-tuned approaches being able to achieve up to 5× better performance compared to some of the existing works.