# EJ-FAT Joint ESnet JLab FPGA Accelerated Transport Load Balancer

arXiv: https://arxiv.org/abs/2303.16351 · HTML: https://mlsanity.com/paper/2303.16351/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 28 Mar 2023.

## Built on by (most cited first, 1 of 1)

- [From Edge to HPC: Investigating Cross-Facility Data Streaming Architectures](https://mlsanity.com/paper/2509.24030/) (2025)

## Abstract (arXiv)

To increase the science rate for high data rates/volumes, Thomas Jefferson National Accelerator Facility (JLab) has partnered with Energy Sciences Network (ESnet) to define an edge to data center traffic shaping / steering transport capability featuring data event-aware network shaping and forwarding. The keystone of this ESnet JLab FPGA Accelerated Transport (EJFAT) is the joint development of a dynamic compute work Load Balancer (LB) of UDP streamed data. The LB is a suite consisting of a Field Programmable Gate Array (FPGA) executing the dynamically configurable, low fixed latency LB data plane featuring real-time packet redirection at high throughput, and a control plane running on the FPGA host computer that monitors network and compute farm telemetry in order to make dynamic decisions for destination compute host redirection / load balancing.