# Statistical Hardware Design With Multi-model Active Learning

arXiv: https://arxiv.org/abs/2303.08054 · HTML: https://mlsanity.com/paper/2303.08054/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 6 of its 50 references that are in the map.
- First posted on arXiv 14 Mar 2023.

## Builds on (most cited first, 6 of 6)

- [Asynchronous Methods for Deep Reinforcement Learning](https://mlsanity.com/paper/1602.01783/) (2016)
- [DRiLLS: Deep Reinforcement Learning for Logic Synthesis](https://mlsanity.com/paper/1911.04021/) (2019)
- [ConfuciuX: Autonomous Hardware Resource Assignment for DNN Accelerators using Reinforcement Learning](https://mlsanity.com/paper/2009.02010/) (2020)
- [On Random Subsampling of Gaussian Process Regression: A Graphon-Based Analysis](https://mlsanity.com/paper/1901.09541/) (2019)
- [Automated Design Space Exploration for optimised Deployment of DNN on Arm Cortex-A CPUs](https://mlsanity.com/paper/2006.05181/) (2020)
- [Rethinking Pareto Frontier for Performance Evaluation of Deep Neural Networks](https://mlsanity.com/paper/2202.09275/) (2022)

## Abstract (arXiv)

With the rising complexity of numerous novel applications that serve our modern society comes the strong need to design efficient computing platforms. Designing efficient hardware is, however, a complex multi-objective problem that deals with multiple parameters and their interactions. Given that there are a large number of parameters and objectives involved in hardware design, synthesizing all possible combinations is not a feasible method to find the optimal solution. One promising approach to tackle this problem is statistical modeling of a desired hardware performance. Here, we propose a model-based active learning approach to solve this problem. Our proposed method uses Bayesian models to characterize various aspects of hardware performance. We also use transfer learning and Gaussian regression bootstrapping techniques in conjunction with active learning to create more accurate models. Our proposed statistical modeling method provides hardware models that are sufficiently accurate to perform design space exploration as well as performance prediction simultaneously. We use our proposed method to perform design space exploration and performance prediction for various hardware setups, such as micro-architecture design and OpenCL kernels for FPGA targets. Our experiments show that the number of samples required to create performance models significantly reduces while maintaining the predictive power of our proposed statistical models. For instance, in our performance prediction setting, the proposed method needs 65% fewer samples to create the model, and in the design space exploration setting, our proposed method can find the best parameter settings by exploring less than 50 samples.