# ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning

arXiv: https://arxiv.org/abs/2303.03372 · HTML: https://mlsanity.com/paper/2303.03372/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 5 of its 13 references that are in the map.
- First posted on arXiv 6 Mar 2023.

## Builds on (most cited first, 5 of 5)

- [Towards Deep Learning Models Resistant to Adversarial Attacks](https://mlsanity.com/paper/1706.06083/) (2017)
- [Adversarially Robust Learning via Entropic Regularization](https://mlsanity.com/paper/2008.12338/) (2020)
- [SAIL: Machine Learning Guided Structural Analysis Attack on Hardware Obfuscation](https://mlsanity.com/paper/1809.10743/) (2018)
- [Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach](https://mlsanity.com/paper/2011.10389/) (2020)
- [UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking](https://mlsanity.com/paper/2012.14938/) (2020)

## Built on by (most cited first, 2 of 2)

- [Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs](https://mlsanity.com/paper/2311.05722/) (2023)
- [ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search](https://mlsanity.com/paper/2406.19549/) (2024)

## Abstract (arXiv)

Oracle-less machine learning (ML) attacks have broken various logic locking schemes. Regular synthesis, which is tailored for area-power-delay optimization, yields netlists where key-gate localities are vulnerable to learning. Thus, we call for security-aware logic synthesis. We propose ALMOST, a framework for adversarial learning to mitigate oracle-less ML attacks via synthesis tuning. ALMOST uses a simulated-annealing-based synthesis recipe generator, employing adversarially trained models that can predict state-of-the-art attacks' accuracies over wide ranges of recipes and key-gate localities. Experiments on ISCAS benchmarks confirm the attacks' accuracies drops to around 50% for ALMOST-synthesized circuits, all while not undermining design optimization.