# An Updated Assessment of Reinforcement Learning for Macro Placement

arXiv: https://arxiv.org/abs/2302.11014 · HTML: https://mlsanity.com/paper/2302.11014/

## Key facts

- Cited by 11 papers in the map (data through 14 Oct 2026).
- Builds on 2 of its 68 references that are in the map.
- First posted on arXiv 21 Feb 2023.

## Builds on (most cited first, 2 of 2)

- [On Joint Learning for Solving Placement and Routing in Chip Design](https://mlsanity.com/paper/2111.00234/) (2021)
- [MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning](https://mlsanity.com/paper/2211.13382/) (2022)

## Built on by (most cited first, 11 of 11)

- [Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms](https://mlsanity.com/paper/2407.15026/) (2024)
- [ORFS-agent: Tool-Using Agents for Chip Design Optimization](https://mlsanity.com/paper/2506.08332/) (2025)
- [Chip Placement with Diffusion Models](https://mlsanity.com/paper/2407.12282/) (2024)
- [That Chip Has Sailed: A Critique of Unfounded Skepticism Around AI for Chip Design](https://mlsanity.com/paper/2411.10053/) (2024)
- [INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search](https://mlsanity.com/paper/2305.13164/) (2023)
- [The False Dawn: Reevaluating Google's Reinforcement Learning for Chip Macro Placement](https://mlsanity.com/paper/2306.09633/) (2023)
- [GOALPlace: Begin with the End in Mind](https://mlsanity.com/paper/2407.04579/) (2024)
- [MAGE: Human-Like Macro Placement via Agentic Multimodal Reasoning](https://mlsanity.com/paper/2607.18536/) (2026)
- [DALI-PD: Diffusion-based Synthetic Layout Heatmap Generation for ML in Physical Design](https://mlsanity.com/paper/2507.10606/) (2025)
- [Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation](https://mlsanity.com/paper/2605.08291/) (2026)
- [CARVE: Breaking Data Barriers in Chip Placement by Harnessing Reusable Expertise](https://mlsanity.com/paper/2609.33106/) (2026)

## Abstract (arXiv)

We provide an improved assessment of Google Brain's deep reinforcement learning approach to macro placement and its updated Circuit Training (CT) implementation in GitHub. A stronger simulated annealing (SA) baseline leverages the "go-with-the-winners" metaheuristic and a multi-threading implementation. We develop and release new public benchmarks in sub-10nm technology: LEF/DEF for Google's 7nm TSMC Ariane protobuf and scaled variants, as well as testcases implemented in the open-source ASAP7 7nm research enablement. We evaluate from-scratch training and fine-tuning results for the latest "AlphaChip" release of Circuit Training, alongside multiple alternative macro placers. We also study the recently-published pre-training guidance in. A commercial place-and-route tool is used to provide "true reward" post-route power, performance and area metrics. All data, evaluation flows and related scripts are publicly available in the MacroPlacement GitHub repository. Our study affords insights into reproducibility and reporting in the research literature, and points out still-missing confirmations (e.g., of CT's scalability and pre-training methodology) that remain open questions for the research community.