# A Bit-Parallel Deterministic Stochastic Multiplier

arXiv: https://arxiv.org/abs/2302.08324 · HTML: https://mlsanity.com/paper/2302.08324/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 0 of its 2 references that are in the map.
- First posted on arXiv 14 Feb 2023.

## Built on by (most cited first, 2 of 2)

- [High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures](https://mlsanity.com/paper/2304.07608/) (2023)
- [ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks](https://mlsanity.com/paper/2407.12638/) (2024)

## Abstract (arXiv)

This paper presents a novel bit-parallel deterministic stochastic multiplier, which improves the area-energy-latency product by up to 10.6×104, while improving the computational error by 32.2%, compared to three prior stochastic multipliers.