# Analog, In-memory Compute Architectures for Artificial Intelligence

arXiv: https://arxiv.org/abs/2302.06417 · HTML: https://mlsanity.com/paper/2302.06417/

## Key facts

- Cited by 1 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 13 Jan 2023.

## Built on by (most cited first, 1 of 1)

- [Efficient Deployment of CNN Models on Multiple In-Memory Computing Units](https://mlsanity.com/paper/2511.04682/) (2025)

## Abstract (arXiv)

This paper presents an analysis of the fundamental limits on energy efficiency in both digital and analog in-memory computing architectures, and compares their performance to single instruction, single data (scalar) machines specifically in the context of machine inference. The focus of the analysis is on how efficiency scales with the size, arithmetic intensity, and bit precision of the computation to be performed. It is shown that analog, in-memory computing architectures can approach arbitrarily high energy efficiency as both the problem size and processor size scales.