# GraphAGILE: An FPGA-based Overlay Accelerator for Low-latency GNN Inference

arXiv: https://arxiv.org/abs/2302.01769 · HTML: https://mlsanity.com/paper/2302.01769/

## Key facts

- Cited by 7 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 2 Feb 2023.

## Built on by (most cited first, 7 of 7)

- [Edge Graph Intelligence: Reciprocally Empowering Edge Networks with Graph Intelligence](https://mlsanity.com/paper/2407.15320/) (2024)
- [Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration](https://mlsanity.com/paper/2308.02749/) (2023)
- [A Single Graph Convolution Is All You Need: Efficient Grayscale Image Classification](https://mlsanity.com/paper/2402.00564/) (2024)
- [GCV-Turbo: End-to-end Acceleration of GNN-based Computer Vision Tasks on FPGA](https://mlsanity.com/paper/2404.07188/) (2024)
- [Physics-Informed Graph Neural Networks for Transverse Momentum Estimation in CMS Trigger Systems](https://mlsanity.com/paper/2507.19205/) (2025)
- [Towards Near-Real-Time Telemetry-Aware Routing with Neural Routing Algorithms](https://mlsanity.com/paper/2604.02927/) (2026)
- [GraphLeap: Decoupling Graph Construction and Convolution for Vision GNN Acceleration on FPGA](https://mlsanity.com/paper/2604.21290/) (2026)

## Abstract (arXiv)

This paper presents GraphAGILE, a domain-specific FPGA-based overlay accelerator for graph neural network (GNN) inference. GraphAGILE consists of (1) a novel unified architecture design with an instruction set, and (2) a compiler built upon the instruction set that can quickly generate optimized code. Due to the proposed instruction set architecture (ISA) and the compiler, GraphAGILE does not require any FPGA reconfiguration when performing inference on various GNN models and input graphs. For the architecture design, we propose a novel hardware module named Adaptive Computation Kernel (ACK), that can execute various computation kernels of GNNs, including general matrix multiplication (GEMM), sparse-dense matrix multiplication (SpDMM) and sampled dense-dense matrix multiplication (SDDMM). The compiler takes the specifications of a GNN model and the graph meta data (e.g., the number of vertices and edges) as input, and generates a sequence of instructions for inference execution. We develop the following compiler optimizations to reduce inference latency: (1) computation order optimization that automatically reorders the computation graph to reduce the total computation complexity, (2) layer fusion that merges adjacent layers to reduce data communication volume, (3) data partitioning with a partition-centric execution scheme that partitions the input graph to fit the available on-chip memory of FPGA, (4) kernel mapping that automatically selects execution mode for ACK, and performs task scheduling to overlap computation with data communication and achieves dynamic load balance. We implement GraphAGILE on a state-of-the-art FPGA platform, Xilinx Alveo U250. GraphAGILE can execute widely used GNN models, including GCN, GAT, GIN, GraphSAGE, SGC and other GNN models supported by GraphGym.