# Security of Electrical, Optical and Wireless On-Chip Interconnects: A Survey

arXiv: https://arxiv.org/abs/2301.09738 · HTML: https://mlsanity.com/paper/2301.09738/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 23 Jan 2023.

## Built on by (most cited first, 2 of 2)

- [Breaking On-Chip Communication Anonymity using Flow Correlation Attacks](https://mlsanity.com/paper/2309.15687/) (2023)
- [Revealing CNN Architectures via Side-Channel Analysis in Dataflow-based Inference Accelerators](https://mlsanity.com/paper/2311.00579/) (2023)

## Abstract (arXiv)

The advancement of manufacturing technologies has enabled the integration of more intellectual property (IP) cores on the same system-on-chip (SoC). Scalable and high throughput on-chip communication architecture has become a vital component in today's SoCs. Diverse technologies such as electrical, wireless, optical, and hybrid are available for on-chip communication with different architectures supporting them. Security of the on-chip communication is crucial because exploiting any vulnerability would be a goldmine for an attacker. In this survey, we provide a comprehensive review of threat models, attacks, and countermeasures over diverse on-chip communication technologies as well as sophisticated architectures.