# Accurate, Low-latency, Efficient SAR Automatic Target Recognition on FPGA

arXiv: https://arxiv.org/abs/2301.01454 · HTML: https://mlsanity.com/paper/2301.01454/

## Key facts

- Cited by 10 papers in the map (data through 14 Oct 2026).
- Builds on 15 of its 47 references that are in the map.
- First posted on arXiv 4 Jan 2023.

## Builds on (most cited first, 15 of 15)

- [Semi-Supervised Classification with Graph Convolutional Networks](https://mlsanity.com/paper/1609.02907/) (2016)
- [Graph Attention Networks](https://mlsanity.com/paper/1710.10903/) (2017)
- [Inductive Representation Learning on Large Graphs](https://mlsanity.com/paper/1706.02216/) (2017)
- [PointNet: Deep Learning on Point Sets for 3D Classification and Segmentation](https://mlsanity.com/paper/1612.00593/) (2016)
- [Squeeze-and-Excitation Networks](https://mlsanity.com/paper/1709.01507/) (2017)
- [PointNet++: Deep Hierarchical Feature Learning on Point Sets in a Metric Space](https://mlsanity.com/paper/1706.02413/) (2017)
- [How Powerful are Graph Neural Networks?](https://mlsanity.com/paper/1810.00826/) (2018)
- [CBAM: Convolutional Block Attention Module](https://mlsanity.com/paper/1807.06521/) (2018)
- [Fast Graph Representation Learning with PyTorch Geometric](https://mlsanity.com/paper/1903.02428/) (2019)
- [Link Prediction Based on Graph Neural Networks](https://mlsanity.com/paper/1802.09691/) (2018)
- [Hierarchical Graph Representation Learning with Differentiable Pooling](https://mlsanity.com/paper/1806.08804/) (2018)
- [HyGCN: A GCN Accelerator with Hybrid Architecture](https://mlsanity.com/paper/2001.02514/) (2020)
- [GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms](https://mlsanity.com/paper/2001.02498/) (2019)
- [Model-Architecture Co-Design for High Performance Temporal GNN Inference on FPGA](https://mlsanity.com/paper/2203.05095/) (2022)
- [HP-GNN: Generating High Throughput GNN Training Implementation on CPU-FPGA Heterogeneous Platform](https://mlsanity.com/paper/2112.11684/) (2021)

## Built on by (most cited first, 10 of 10)

- [Realistic Scatterer Based Adversarial Attacks on SAR Image Classifiers](https://mlsanity.com/paper/2312.02912/) (2023)
- [Benchmarking Deep Learning Classifiers for SAR Automatic Target Recognition](https://mlsanity.com/paper/2312.06940/) (2023)
- [Exploiting On-chip Heterogeneity of Versal Architecture for GNN Inference Acceleration](https://mlsanity.com/paper/2308.02749/) (2023)
- [A Single Graph Convolution Is All You Need: Efficient Grayscale Image Classification](https://mlsanity.com/paper/2402.00564/) (2024)
- [FPGA-Based Neural Network Accelerators for Space Applications: A Survey](https://mlsanity.com/paper/2504.16173/) (2025)
- [FPGA-Enabled Machine Learning Applications in Earth Observation: A Systematic Review](https://mlsanity.com/paper/2506.03938/) (2025)
- [Graph Neural Network for Accurate and Low-complexity SAR ATR](https://mlsanity.com/paper/2305.07119/) (2023)
- [VTR: An Optimized Vision Transformer for SAR ATR Acceleration on FPGA](https://mlsanity.com/paper/2404.04527/) (2024)
- [Uncertainty-Aware SAR ATR: Defending Against Adversarial Attacks via Bayesian Neural Networks](https://mlsanity.com/paper/2403.18318/) (2024)
- [Evaluating Four FPGA-accelerated Space Use Cases based on Neural Network Algorithms for On-board Inference](https://mlsanity.com/paper/2603.14091/) (2026)

## Abstract (arXiv)

Synthetic aperture radar (SAR) automatic target recognition (ATR) is the key technique for remote-sensing image recognition. The state-of-the-art convolutional neural networks (CNNs) for SAR ATR suffer from high computation cost and large memory footprint, making them unsuitable to be deployed on resource-limited platforms, such as small/micro satellites. In this paper, we propose a comprehensive GNN-based model-architecture co-design on FPGA to address the above issues. Model design: we design a novel graph neural network (GNN) for SAR ATR. The proposed GNN model incorporates GraphSAGE layer operators and attention mechanism, achieving comparable accuracy as the state-of-the-art work with near 1/100 computation cost. Then, we propose a pruning approach including weight pruning and input pruning. While weight pruning through lasso regression reduces most parameters without accuracy drop, input pruning eliminates most input pixels with negligible accuracy drop. Architecture design: to fully unleash the computation parallelism within the proposed model, we develop a novel unified hardware architecture that can execute various computation kernels (feature aggregation, feature transformation, graph pooling). The proposed hardware design adopts the Scatter-Gather paradigm to efficiently handle the irregular computation patterns of various computation kernels. We deploy the proposed design on an embedded FPGA (AMD Xilinx ZCU104) and evaluate the performance using MSTAR dataset. Compared with the state-of-the-art CNNs, the proposed GNN achieves comparable accuracy with 1/3258 computation cost and 1/83 model size. Compared with the state-of-the-art CPU/GPU, our FPGA accelerator achieves 14.8×/2.5× speedup (latency) and is 62×/39× more energy efficient.