# A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface

arXiv: https://arxiv.org/abs/2212.04320 · HTML: https://mlsanity.com/paper/2212.04320/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 1 of its 9 references that are in the map.
- First posted on arXiv 23 Nov 2022.

## Builds on (most cited first, 1 of 1)

- [Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune](https://mlsanity.com/paper/2104.06377/) (2021)

## Abstract (arXiv)

Performing data-intensive tasks in the von Neumann architecture is challenging to achieve both high performance and power efficiency due to the memory wall bottleneck. Computing-in-memory (CiM) is a promising mitigation approach by enabling parallel in-situ multiply-accumulate (MAC) operations within the memory with support from the peripheral interface and datapath. SRAM-based charge-domain CiM (CD-CiM) has shown its potential of enhanced power efficiency and computing accuracy. However, existing SRAM-based CD-CiM faces scaling challenges to meet the throughput requirement of high-performance multi-bit-quantization applications. This paper presents an SRAM-based high-throughput ReLU-optimized CD-CiM macro. It is capable of completing MAC and ReLU of two signed 8b vectors in one CiM cycle with only one A/D conversion. Along with non-linearity compensation for the analog computing and A/D conversion interfaces, this work achieves 51.2GOPS throughput and 10.3TOPS/W energy efficiency, while showing 88.6% accuracy in the CIFAR-10 dataset.