# Sparse Hamming Graph: A Customizable Network-on-Chip Topology

arXiv: https://arxiv.org/abs/2211.13980 · HTML: https://mlsanity.com/paper/2211.13980/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 25 Nov 2022.

## Built on by (most cited first, 2 of 2)

- [Demystifying Chains, Trees, and Graphs of Thoughts](https://mlsanity.com/paper/2401.14295/) (2024)
- [Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads](https://mlsanity.com/paper/2403.19073/) (2024)

## Abstract (arXiv)

Chips with hundreds to thousands of cores require scalable networks-on-chip (NoCs). Customization of the NoC topology is necessary to reach the diverse design goals of different chips. We introduce sparse Hamming graph, a novel NoC topology with an adjustable costperformance trade-off that is based on four NoC topology design principles we identified. To efficiently customize this topology, we develop a toolchain that leverages approximate floorplanning and link routing to deliver fast and accurate cost and performance predictions. We demonstrate how to use our methodology to achieve desired cost-performance trade-offs while outperforming established topologies in cost, performance, or both.