# MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning

arXiv: https://arxiv.org/abs/2211.13382 · HTML: https://mlsanity.com/paper/2211.13382/

## Key facts

- Cited by 43 papers in the map (data through 14 Oct 2026).
- Builds on 10 of its 43 references that are in the map.
- First posted on arXiv 24 Nov 2022.

## Builds on (most cited first, 10 of 10)

- [Proximal Policy Optimization Algorithms](https://mlsanity.com/paper/1707.06347/) (2017)
- [Semi-Supervised Classification with Graph Convolutional Networks](https://mlsanity.com/paper/1609.02907/) (2016)
- [On Joint Learning for Solving Placement and Routing in Chip Design](https://mlsanity.com/paper/2111.00234/) (2021)
- [The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology](https://mlsanity.com/paper/1904.05442/) (2019)
- [Placement in Integrated Circuits using Cyclic Reinforcement Learning and Simulated Annealing](https://mlsanity.com/paper/2011.07577/) (2020)
- [Attention Routing: track-assignment detailed routing using attention-based reinforcement learning](https://mlsanity.com/paper/2004.09473/) (2020)
- [Delving into Macro Placement with Reinforcement Learning](https://mlsanity.com/paper/2109.02587/) (2021)
- [Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview](https://mlsanity.com/paper/2202.13564/) (2022)
- [Flexible Multiple-Objective Reinforcement Learning for Chip Placement](https://mlsanity.com/paper/2204.06407/) (2022)
- [Guiding Global Placement With Reinforcement Learning](https://mlsanity.com/paper/2109.02631/) (2021)

## Built on by (most cited first, 30 of 43)

- [AnalogCoder: Analog Circuit Design via Training-Free Code Generation](https://mlsanity.com/paper/2405.14918/) (2024)
- [ChiPFormer: Transferable Chip Placement via Offline Decision Transformer](https://mlsanity.com/paper/2306.14744/) (2023)
- [LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation](https://mlsanity.com/paper/2401.12224/) (2023)
- [DeepGate2: Functionality-Aware Circuit Representation Learning](https://mlsanity.com/paper/2305.16373/) (2023)
- [Macro Placement by Wire-Mask-Guided Black-Box Optimization](https://mlsanity.com/paper/2306.16844/) (2023)
- [Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms](https://mlsanity.com/paper/2407.15026/) (2024)
- [LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation](https://mlsanity.com/paper/2406.05250/) (2024)
- [An Updated Assessment of Reinforcement Learning for Macro Placement](https://mlsanity.com/paper/2302.11014/) (2023)
- [Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization](https://mlsanity.com/paper/2401.12205/) (2024)
- [Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer](https://mlsanity.com/paper/2412.07167/) (2024)
- [Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs](https://mlsanity.com/paper/2405.06758/) (2024)
- [Revolution or Hype? Seeking the Limits of Large Models in Hardware Design](https://mlsanity.com/paper/2509.04905/) (2025)
- [INSIGHT: Universal Neural Simulator for Analog Circuits Harnessing Autoregressive Transformers](https://mlsanity.com/paper/2407.07346/) (2024)
- [A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design](https://mlsanity.com/paper/2309.03208/) (2023)
- [Evolution of Optimization Algorithms for Global Placement via Large Language Models](https://mlsanity.com/paper/2504.17801/) (2025)
- [PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modeling](https://mlsanity.com/paper/2403.00012/) (2024)
- [Chip Placement with Diffusion Models](https://mlsanity.com/paper/2407.12282/) (2024)
- [That Chip Has Sailed: A Critique of Unfounded Skepticism Around AI for Chip Design](https://mlsanity.com/paper/2411.10053/) (2024)
- [Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning](https://mlsanity.com/paper/2411.15212/) (2024)
- [BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement](https://mlsanity.com/paper/2510.23472/) (2025)
- [Learning Solution-Aware Transformers for Efficiently Solving Quadratic Assignment Problem](https://mlsanity.com/paper/2406.09899/) (2024)
- [INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search](https://mlsanity.com/paper/2305.13164/) (2023)
- [Enhancing Reinforcement Learning for the Floorplanning of Analog ICs with Beam Search](https://mlsanity.com/paper/2505.05059/) (2025)
- [Toward Reinforcement Learning-based Rectilinear Macro Placement Under Human Constraints](https://mlsanity.com/paper/2311.03383/) (2023)
- [Escaping Local Optima in Global Placement](https://mlsanity.com/paper/2402.18311/) (2024)
- [RoutePlacer: An End-to-End Routability-Aware Placer with Graph Neural Network](https://mlsanity.com/paper/2406.02651/) (2024)
- [See it to Place it: Evolving Macro Placements with Vision-Language Models](https://mlsanity.com/paper/2603.28733/) (2026)
- [Physics-Guided Geometric Diffusion for Macro Placement Generation](https://mlsanity.com/paper/2605.16451/) (2026)
- [Order Matters: Unveiling the Hidden Impact of Macro Placement Sequences via Proxy-Guided LLM Evolution](https://mlsanity.com/paper/2606.08904/) (2026)
- [Chiplet Placement Order Exploration Based on Learning to Rank with Graph Representation](https://mlsanity.com/paper/2404.04943/) (2024)

## Abstract (arXiv)

Placement is an essential task in modern chip design, aiming at placing millions of circuit modules on a 2D chip canvas. Unlike the human-centric solution, which requires months of intense effort by hardware engineers to produce a layout to minimize delay and energy consumption, deep reinforcement learning has become an emerging autonomous tool. However, the learning-centric method is still in its early stage, impeded by a massive design space of size ten to the order of a few thousand. This work presents MaskPlace to automatically generate a valid chip layout design within a few hours, whose performance can be superior or comparable to recent advanced approaches. It has several appealing benefits that prior arts do not have. Firstly, MaskPlace recasts placement as a problem of learning pixel-level visual representation to comprehensively describe millions of modules on a chip, enabling placement in a high-resolution canvas and a large action space. It outperforms recent methods that represent a chip as a hypergraph. Secondly, it enables training the policy network by an intuitive reward function with dense reward, rather than a complicated reward function with sparse reward from previous methods. Thirdly, extensive experiments on many public benchmarks show that MaskPlace outperforms existing RL approaches in all key performance metrics, including wirelength, congestion, and density. For example, it achieves 60%-90% wirelength reduction and guarantees zero overlaps. We believe MaskPlace can improve AI-assisted chip layout design. The deliverables are released at https://laiyao1.github.io/maskplace.