# Reliability-Aware Deployment of DNNs on In-Memory Analog Computing Architectures

arXiv: https://arxiv.org/abs/2211.00590 · HTML: https://mlsanity.com/paper/2211.00590/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 3 of its 5 references that are in the map.
- First posted on arXiv 2 Oct 2022.

## Builds on (most cited first, 3 of 3)

- [An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devices](https://mlsanity.com/paper/2105.13904/) (2021)
- [Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architectures](https://mlsanity.com/paper/2201.12480/) (2022)
- [MRAM-based Analog Sigmoid Function for In-memory Computing](https://mlsanity.com/paper/2204.09918/) (2022)

## Abstract (arXiv)

Conventional in-memory computing (IMC) architectures consist of analog memristive crossbars to accelerate matrix-vector multiplication (MVM), and digital functional units to realize nonlinear vector (NLV) operations in deep neural networks (DNNs). These designs, however, require energy-hungry signal conversion units which can dissipate more than 95% of the total power of the system. In-Memory Analog Computing (IMAC) circuits, on the other hand, remove the need for signal converters by realizing both MVM and NLV operations in the analog domain leading to significant energy savings. However, they are more susceptible to reliability challenges such as interconnect parasitic and noise. Here, we introduce a practical approach to deploy large matrices in DNNs onto multiple smaller IMAC subarrays to alleviate the impacts of noise and parasitics while keeping the computation in the analog domain.