# Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization

arXiv: https://arxiv.org/abs/2210.14259 · HTML: https://mlsanity.com/paper/2210.14259/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 25 Oct 2022.

## Built on by (most cited first, 2 of 2)

- [RoutePlacer: An End-to-End Routability-Aware Placer with Graph Neural Network](https://mlsanity.com/paper/2406.02651/) (2024)
- [OmniLayout: A Schematic-Coupled Multimodal Benchmark for Constraint-Aware Geometric Reasoning in PCB Layout](https://mlsanity.com/paper/2607.03261/) (2026)

## Abstract (arXiv)

Packaging has become a crucial process due to the paradigm shift of More than Moore. Addressing manufacturing and yield issues is a significant challenge for modern layout algorithms. We propose to use printed circuit board (PCB) placement as a benchmark for the packaging problem. A maximum-margin formulation is devised to improve the separation between nets. Our framework includes seed layout proposals, a coordinate descent-based procedure to optimize routability, and a mixed-integer linear programming method to legalize the layout. We perform an extensive study with 14 PCB designs and an open-source router. We show that the placements produced by NS-place improve routed wirelength by up to 25%, reduce the number of vias by up to 50%, and reduce the number of DRVs by 79% compared to manual and wirelength-minimal placements.