# Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization

arXiv: https://arxiv.org/abs/2210.03916 · HTML: https://mlsanity.com/paper/2210.03916/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 2 of its 24 references that are in the map.
- First posted on arXiv 8 Oct 2022.

## Builds on (most cited first, 2 of 2)

- [Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference](https://mlsanity.com/paper/1712.05877/) (2017)
- [Control Variate Approximation for DNN Accelerators](https://mlsanity.com/paper/2102.09642/) (2021)

## Abstract (arXiv)

In this paper, two approximate 3*3 multipliers are proposed and the synthesis results of the ASAP-7nm process library justify that they can reduce the area by 31.38% and 36.17%, and the power consumption by 36.73% and 35.66% compared with the exact multiplier, respectively. They can be aggregated with a 2*2 multiplier to produce an 8*8 multiplier with low error rate based on the distribution of DNN weights. We propose a hardware-driven software co-optimization method to improve the DNN accuracy by retraining. Based on the proposed two approximate 3-bit multipliers, three approximate 8-bit multipliers with low error-rate are designed for DNNs. Compared with the exact 8-bit unsigned multiplier, our design can achieve a significant advantage over other approximate multipliers on the public dataset.