# Mining SoC Message Flows with Attention Model

arXiv: https://arxiv.org/abs/2209.07929 · HTML: https://mlsanity.com/paper/2209.07929/

## Key facts

- No citing papers in the map yet (data through 14 Oct 2026).
- Builds on 8 of its 29 references that are in the map.
- First posted on arXiv 12 Sep 2022.

## Builds on (most cited first, 8 of 8)

- [Attention Is All You Need](https://mlsanity.com/paper/1706.03762/) (2017)
- [BERT: Pre-training of Deep Bidirectional Transformers for Language Understanding](https://mlsanity.com/paper/1810.04805/) (2018)
- [DistilBERT, a distilled version of BERT: smaller, faster, cheaper and lighter](https://mlsanity.com/paper/1910.01108/) (2019)
- [Learning Concise Models from Long Execution Traces](https://mlsanity.com/paper/2001.05230/) (2020)
- [Mining Message Flows from System-on-Chip Execution Traces](https://mlsanity.com/paper/2005.11221/) (2020)
- [Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs](https://mlsanity.com/paper/2005.01574/) (2020)
- [A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug](https://mlsanity.com/paper/2005.02550/) (2020)
- [Active Learning of Abstract System Models from Traces using Model Checking [Extended]](https://mlsanity.com/paper/2112.05990/) (2021)

## Abstract (arXiv)

High-quality system-level message flow specifications are necessary for comprehensive validation of system-on-chip (SoC) designs. However, manual development and maintenance of such specifications are daunting tasks. We propose a disruptive method that utilizes deep sequence modeling with the attention mechanism to infer accurate flow specifications from SoC communication traces. The proposed method can overcome the inherent complexity of SoC traces induced by the concurrent executions of SoC designs that existing mining tools often find extremely challenging. We conduct experiments on five highly concurrent traces and find that the proposed approach outperforms several existing state-of-the-art trace mining tools.