# A Deep-Learning-Aided Pipeline for Efficient Post-Silicon Tuning

arXiv: https://arxiv.org/abs/2207.00336 · HTML: https://mlsanity.com/paper/2207.00336/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 2 of its 6 references that are in the map.
- First posted on arXiv 1 Jul 2022.

## Builds on (most cited first, 2 of 2)

- [Feature Selection Using Batch-Wise Attenuation and Feature Mask Normalization](https://mlsanity.com/paper/2010.13631/) (2020)
- [Self-Learning Tuning for Post-Silicon Validation](https://mlsanity.com/paper/2111.08995/) (2021)

## Built on by (most cited first, 2 of 2)

- [Deep Feature Selection Using a Novel Complementary Feature Mask](https://mlsanity.com/paper/2209.12282/) (2022)
- [Experts in the Loop: Conditional Variable Selection for Accelerating Post-Silicon Analysis Based on Deep Learning](https://mlsanity.com/paper/2209.15249/) (2022)

## Abstract (arXiv)

In post-silicon validation, tuning is to find the values for the tuning knobs, potentially as a function of process parameters and/or known operating conditions. In this sense, an more efficient tuning requires identifying the most critical tuning knobs and process parameters in terms of a given figure-of-merit for a Device Under Test (DUT). This is often manually conducted by experienced experts. However, with increasingly complex chips, manual inspection on a large amount of raw variables has become more challenging. In this work, we leverage neural networks to efficiently select the most relevant variables and present a corresponding deep-learning-aided pipeline for efficient tuning.