# Two-stage Human Activity Recognition on Microcontrollers with Decision Trees and CNNs

arXiv: https://arxiv.org/abs/2206.07652 · HTML: https://mlsanity.com/paper/2206.07652/

## Key facts

- Cited by 2 papers in the map (data through 14 Oct 2026).
- Builds on 7 of its 15 references that are in the map.
- First posted on arXiv 7 Jun 2022.

## Builds on (most cited first, 7 of 7)

- [Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference](https://mlsanity.com/paper/1712.05877/) (2017)
- [BranchyNet: Fast Inference via Early Exiting from Deep Neural Networks](https://mlsanity.com/paper/1709.01686/) (2017)
- [Runtime Configurable Deep Neural Networks for Energy-Accuracy Trade-off](https://mlsanity.com/paper/1607.05418/) (2016)
- [Ultra-compact Binary Neural Networks for Human Activity Recognition on RISC-V Processors](https://mlsanity.com/paper/2205.12781/) (2022)
- [Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node](https://mlsanity.com/paper/2007.08952/) (2020)
- [TCN Mapping Optimization for Ultra-Low Power Time-Series Edge Inference](https://mlsanity.com/paper/2203.12925/) (2022)
- [Adaptive Random Forests for Energy-Efficient Inference on Microcontrollers](https://mlsanity.com/paper/2205.13838/) (2022)

## Built on by (most cited first, 2 of 2)

- [AALF: Almost Always Linear Forecasting](https://mlsanity.com/paper/2409.10142/) (2024)
- [Efficient Multi-stage Inference on Tabular Data](https://mlsanity.com/paper/2303.11580/) (2023)

## Abstract (arXiv)

Human Activity Recognition (HAR) has become an increasingly popular task for embedded devices such as smartwatches. Most HAR systems for ultra-low power devices are based on classic Machine Learning (ML) models, whereas Deep Learning (DL), although reaching state-of-the-art accuracy, is less popular due to its high energy consumption, which poses a significant challenge for battery-operated and resource-constrained devices. In this work, we bridge the gap between on-device HAR and DL thanks to a hierarchical architecture composed of a decision tree (DT) and a one dimensional Convolutional Neural Network (1D CNN). The two classifiers operate in a cascaded fashion on two different sub-tasks: the DT classifies only the easiest activities, while the CNN deals with more complex ones. With experiments on a state-of-the-art dataset and targeting a single-core RISC-V MCU, we show that this approach allows to save up to 67.7% energy w.r.t. a "stand-alone" DL architecture at iso-accuracy. Additionally, the two-stage system either introduces a negligible memory overhead (up to 200 B) or on the contrary, reduces the total memory occupation.