# Automated Circuit Sizing with Multi-objective Optimization based on Differential Evolution and Bayesian Inference

arXiv: https://arxiv.org/abs/2206.02391 · HTML: https://mlsanity.com/paper/2206.02391/

## Key facts

- Cited by 3 papers in the map (data through 14 Oct 2026).
- Builds on 5 of its 51 references that are in the map.
- First posted on arXiv 6 Jun 2022.

## Builds on (most cited first, 5 of 5)

- [GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning](https://mlsanity.com/paper/2005.00406/) (2020)
- [Learning to Design Circuits](https://mlsanity.com/paper/1812.02734/) (2018)
- [Two-Archive Evolutionary Algorithm for Constrained Multi-Objective Optimization](https://mlsanity.com/paper/1711.07907/) (2017)
- [Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network](https://mlsanity.com/paper/1912.00402/) (2019)
- [Multi-objective multi-generation Gaussian process optimizer for design optimization](https://mlsanity.com/paper/1907.00250/) (2019)

## Built on by (most cited first, 3 of 3)

- [HeaRT: A Hierarchical Circuit Reasoning Tree-Based Agentic Framework for AMS Design Optimization](https://mlsanity.com/paper/2511.19669/) (2025)
- [ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration](https://mlsanity.com/paper/2608.04999/) (2026)
- [Deterministic Pareto-Optimal Policy Synthesis for Multi-Objective Reinforcement Learning](https://mlsanity.com/paper/2606.26397/) (2026)

## Abstract (arXiv)

With the ever increasing complexity of specifications, manual sizing for analog circuits recently became very challenging. Especially for innovative, large-scale circuits designs, with tens of design variables, operating conditions and conflicting objectives to be optimized, design engineers spend many weeks, running time-consuming simulations, in their attempt at finding the right configuration. Recent years brought machine learning and optimization techniques to the field of analog circuits design, with evolutionary algorithms and Bayesian models showing good results for circuit sizing. In this context, we introduce a design optimization method based on Generalized Differential Evolution 3 (GDE3) and Gaussian Processes (GPs). The proposed method is able to perform sizing for complex circuits with a large number of design variables and many conflicting objectives to be optimized. While state-of-the-art methods reduce multi-objective problems to single-objective optimization and potentially induce a prior bias, we search directly over the multi-objective space using Pareto dominance and ensure that diverse solutions are provided to the designers to choose from. To the best of our knowledge, the proposed method is the first to specifically address the diversity of the solutions, while also focusing on minimizing the number of simulations required to reach feasible configurations. We evaluate the introduced method on two voltage regulators showing different levels of complexity and we highlight that the proposed innovative candidate selection method and survival policy leads to obtaining feasible solutions, with a high degree of diversity, much faster than with GDE3 or Bayesian Optimization-based algorithms.