# Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases arXiv: https://arxiv.org/abs/2205.14664 ยท HTML: https://mlsanity.com/paper/2205.14664/ ## Key facts - Cited by 1 papers in the map (data through 14 Oct 2026). - Builds on 46 of its 188 references that are in the map. - First posted on arXiv 29 May 2022. ## Builds on (most cited first, 30 of 46) - [Show and Tell: A Neural Image Caption Generator](https://mlsanity.com/paper/1411.4555/) (2014) - [Long-term Recurrent Convolutional Networks for Visual Recognition and Description](https://mlsanity.com/paper/1411.4389/) (2014) - [Streaming End-to-end Speech Recognition For Mobile Devices](https://mlsanity.com/paper/1811.06621/) (2018) - [Long Short-Term Memory Based Recurrent Neural Network Architectures for Large Vocabulary Speech Recognition](https://mlsanity.com/paper/1402.1128/) (2014) - [Exploring Architectures, Data and Units For Streaming End-to-End Speech Recognition with RNN-Transducer](https://mlsanity.com/paper/1801.00841/) (2018) - [Improving RNN Transducer Modeling for End-to-End Speech Recognition](https://mlsanity.com/paper/1909.12415/) (2019) - [RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing](https://mlsanity.com/paper/1912.12953/) (2019) - [TensorDIMM: A Practical Near-Memory Processing Architecture for Embeddings and Tensor Operations in Deep Learning](https://mlsanity.com/paper/1908.03072/) (2019) - [RecSSD: Near Data Processing for Solid State Drive Based Recommendation Inference](https://mlsanity.com/paper/2102.00075/) (2021) - [Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks](https://mlsanity.com/paper/1805.03718/) (2018) - [A Modern Primer on Processing in Memory](https://mlsanity.com/paper/2012.03112/) (2020) - [Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks](https://mlsanity.com/paper/2109.14320/) (2021) - [Processing Data Where It Makes Sense: Enabling In-Memory Computation](https://mlsanity.com/paper/1903.03988/) (2019) - [GraphR: Accelerating Graph Processing Using ReRAM](https://mlsanity.com/paper/1708.06248/) (2017) - [SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems](https://mlsanity.com/paper/2104.07582/) (2021) - [Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-in-Memory Hardware](https://mlsanity.com/paper/2110.01709/) (2021) - [FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator](https://mlsanity.com/paper/2106.09144/) (2021) - [GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies](https://mlsanity.com/paper/1711.01177/) (2017) - [TitAnt: Online Real-time Transaction Fraud Detection in Ant Financial](https://mlsanity.com/paper/1906.07407/) (2019) - [NATSA: A Near-Data Processing Accelerator for Time Series Analysis](https://mlsanity.com/paper/2010.02079/) (2020) - [DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks](https://mlsanity.com/paper/2105.03725/) (2021) - [GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis](https://mlsanity.com/paper/2009.07692/) (2020) - [SynCron: Efficient Synchronization Support for Near-Data-Processing Architectures](https://mlsanity.com/paper/2101.07557/) (2021) - [Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture](https://mlsanity.com/paper/2105.03814/) (2021) - [NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling](https://mlsanity.com/paper/2009.08241/) (2020) - [QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips](https://mlsanity.com/paper/2105.08955/) (2021) - [FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applications](https://mlsanity.com/paper/2106.06433/) (2021) - [Mitigating Edge Machine Learning Inference Bottlenecks: An Empirical Study on Accelerating Google Edge Models](https://mlsanity.com/paper/2103.00768/) (2021) - [Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM](https://mlsanity.com/paper/1611.09988/) (2016) - [D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput](https://mlsanity.com/paper/1808.04286/) (2018) ## Built on by (most cited first, 1 of 1) - [PIM-Opt: Demystifying Distributed Optimization Algorithms on a Real-World Processing-In-Memory System](https://mlsanity.com/paper/2404.07164/) (2024) ## Abstract (arXiv) Today's computing systems require moving data back-and-forth between computing resources (e.g., CPUs, GPUs, accelerators) and off-chip main memory so that computation can take place on the data. Unfortunately, this data movement is a major bottleneck for system performance and energy consumption. One promising execution paradigm that alleviates the data movement bottleneck in modern and emerging applications is processing-in-memory (PIM), where the cost of data movement to/from main memory is reduced by placing computation capabilities close to memory. Naively employing PIM to accelerate data-intensive workloads can lead to sub-optimal performance due to the many design constraints PIM substrates impose. Therefore, many recent works co-design specialized PIM accelerators and algorithms to improve performance and reduce the energy consumption of (i) applications from various application domains; and (ii) various computing environments, including cloud systems, mobile systems, and edge devices. We showcase the benefits of co-designing algorithms and hardware in a way that efficiently takes advantage of the PIM paradigm for two modern data-intensive applications: (1) machine learning inference models for edge devices and (2) hybrid transactional/analytical processing databases for cloud systems. We follow a two-step approach in our system design. In the first step, we extensively analyze the computation and memory access patterns of each application to gain insights into its hardware/software requirements and major sources of performance and energy bottlenecks in processor-centric systems. In the second step, we leverage the insights from the first step to co-design algorithms and hardware accelerators to enable high-performance and energy-efficient data-centric architectures for each application.