# TinyIREE: An ML Execution Environment for Embedded Systems from Compilation to Deployment

arXiv: https://arxiv.org/abs/2205.14479 · HTML: https://mlsanity.com/paper/2205.14479/

## Key facts

- Cited by 12 papers in the map (data through 14 Oct 2026).
- First posted on arXiv 28 May 2022.

## Built on by (most cited first, 12 of 12)

- [Embodied Foundation Models at the Edge: A Survey of Deployment Constraints and Mitigation Strategies](https://mlsanity.com/paper/2603.16952/) (2026)
- [MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devices](https://mlsanity.com/paper/2410.08855/) (2024)
- [Fuzzy PyTorch: Rapid Numerical Variability Evaluation for Deep Learning Models](https://mlsanity.com/paper/2605.25991/) (2026)
- [Productive Reproducible Workflows for DNNs: A Case Study for Industrial Defect Detection](https://mlsanity.com/paper/2206.09359/) (2022)
- [Ariel-ML: Computing Parallelization with Embedded Rust for Neural Networks on Heterogeneous Multi-core Microcontrollers](https://mlsanity.com/paper/2512.09800/) (2025)
- [Full-stack evaluation of Machine Learning inference workloads for RISC-V systems](https://mlsanity.com/paper/2405.15380/) (2024)
- [Fake Runs, Real Fixes -- Analyzing xPU Performance Through Simulation](https://mlsanity.com/paper/2503.14781/) (2025)
- [A High-Level Compiler Integration Approach for Deep Learning Accelerators Supporting Abstraction and Optimization](https://mlsanity.com/paper/2507.04828/) (2025)
- [XTC, A Research Platform for Optimizing AI Workload Operators](https://mlsanity.com/paper/2512.16512/) (2025)
- [Optimizing Tensor Train Decomposition in DNNs for RISC-V Architectures Using Design Space Exploration and Compiler Optimizations](https://mlsanity.com/paper/2602.01996/) (2026)
- [Meganeura: Portable GPU Training and Inference through Vulkan and Metal](https://mlsanity.com/paper/2608.01563/) (2026)
- [RISC-V and machine learning: a survey](https://mlsanity.com/paper/2609.20677/) (2026)

## Abstract (arXiv)

Machine learning model deployment for training and execution has been an important topic for industry and academic research in the last decade. Much of the attention has been focused on developing specific toolchains to support acceleration hardware. In this paper, we present IREE, a unified compiler and runtime stack with the explicit goal to scale down machine learning programs to the smallest footprints for mobile and edge devices, while maintaining the ability to scale up to larger deployment targets. IREE adopts a compiler-based approach and optimizes for heterogeneous hardware accelerators through the use of the MLIR compiler infrastructure which provides the means to quickly design and implement multi-level compiler intermediate representations (IR). More specifically, this paper is focused on TinyIREE, which is a set of deployment options in IREE that accommodate the limited memory and computation resources in embedded systems and bare-metal platforms, while also demonstrating IREE's intuitive workflow that generates workloads for different ISA extensions and ABIs through LLVM.